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Searched refs:DMA (Results 1 – 25 of 89) sorted by relevance

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/openbmc/u-boot/drivers/dma/
H A DKconfig1 menu "DMA Support"
3 config DMA config
4 bool "Enable Driver Model for DMA drivers"
7 Enable driver model for DMA. DMA engines can do
11 etc Drivers provide methods to access the DMA devices
16 bool "Enable DMA channels support"
17 depends on DMA
19 Enable channels support for DMA. Some DMA controllers have multiple
23 bool "Enable the sandbox DMA test driver"
24 depends on DMA && DMA_CHANNELS && SANDBOX
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/openbmc/qemu/docs/specs/
H A Dedu.rst23 ``dma_mask`` makes the virtual device work with DMA addresses with the given
78 0x80 (RW) : DMA source address
79 Where to perform the DMA from.
81 0x88 (RW) : DMA destination address
82 Where to perform the DMA to.
84 0x90 (RW) : DMA transfer count
85 The size of the area to perform the DMA on.
87 0x98 (RW) : DMA command register
95 raise interrupt 0x100 after finishing the DMA
109 DMA controller
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H A Dfw_cfg.rst41 As of QEMU v2.9, writes are reinstated, but only through the DMA
56 * Read/Write (writes ignored as of QEMU v2.4, but see the DMA interface)
90 * DMA Address IOport: 0x514
95 * DMA Address address: Base + 16 (8 bytes)
118 If the DMA interface is available, then reading the DMA Address
128 - Bit 1: DMA interface.
169 the DMA interface in QEMU v2.9+)
172 through the DMA interface in QEMU v2.9+)
179 Guest-side DMA Interface
182 If bit 1 of the feature bitmap is set, the DMA interface is present. This does
H A Drocker.rst115 Interrupts, DMA, and Endianness
153 DMA Operations
156 DMA operations are used for packet DMA to/from the CPU, command and event
159 notification method for device-originating events. Each DMA operation has a
161 allocated from contiguous host DMA-able memory and registers specify the rings
322 interrupt generation, and DMA operations::
338 To test basic DMA operations, allocate a DMA-able host buffer and put the
400 Other properties for front-panel ports are available via DMA CMD descriptors::
526 in the DMA RX ring. Likewise, host CPU originating packets destined to egress
527 on switch ports are scheduled by software using the DMA TX ring.
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/openbmc/u-boot/doc/
H A DREADME.arm-caches20 Memory to Peripheral DMA:
21 - Flush the buffer after the MPU writes the data and before the DMA is
24 Peripheral to Memory DMA:
25 - Invalidate the buffer before starting the DMA. In case there are any dirty
26 lines from the DMA buffer in the cache, subsequent cache-line replacements
27 may corrupt the buffer in memory while the DMA is still going on. Cache-line
29 into the cache while the DMA is going on.
30 - Invalidate the buffer after the DMA is complete and before the MPU reads
31 it. This may be needed in addition to the invalidation before the DMA
34 happens with the DMA buffer while DMA is going on we have a coherency problem.
[all …]
H A DREADME.fsl-trustzone-components23 such as processors and DMA-equipped peripherals.
H A DREADME.N121340 - Optional 1D/2D DMA engine.
/openbmc/qemu/hw/dma/
H A Dtrace-events10 ledma_memory_read(uint64_t addr, int len) "DMA read addr 0x%"PRIx64 " len %d"
11 ledma_memory_write(uint64_t addr, int len) "DMA write addr 0x%"PRIx64 " len %d"
14 espdma_memory_read(uint32_t addr, int len) "DMA read addr 0x%08x len %d"
15 espdma_memory_write(uint32_t addr, int len) "DMA write addr 0x%08x len %d"
18 sparc32_dma_enable_raise(void) "Raise DMA enable"
19 sparc32_dma_enable_lower(void) "Lower DMA enable"
22 i8257_unregistered_dma(int nchan, int dma_pos, int dma_len) "unregistered DMA channel used nchan=%d…
27 pl330_dmaend(void) "DMA ending"
28 pl330_dmago(void) "DMA run"
/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Domap_serial.txt19 - dmas : DMA specifier, consisting of a phandle to the DMA controller
20 node and a DMA channel number.
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dstmmac.txt21 - snps,fixed-burst Program the DMA to use the fixed burst mode
22 - snps,mixed-burst Program the DMA to use the mixed burst mode
23 - snps,force_thresh_dma_mode Force DMA to use the threshold mode for
25 - snps,force_sf_dma_mode Force DMA to use the Store and Forward
H A Dsnps,dwc-qos-ethernet.txt116 - snps,txpbl: DMA Programmable burst length for the TX DMA
117 - snps,rxpbl: DMA Programmable burst length for the RX DMA
/openbmc/qemu/docs/devel/
H A Dvfio-iommufd.rst8 interface for user space drivers to propagate their DMA mappings to kernel
72 * DMA Mapping flow
75 2. VFIO populates DMA map/unmap via the container BEs
142 P2P DMA
145 PCI p2p DMA is unsupported as IOMMUFD doesn't support mapping hardware PCI
/openbmc/u-boot/board/freescale/m547xevb/
H A DREADME29 - drivers/dma/MCD_dmaApi.c DMA API functions
30 - drivers/dma/MCD_tasks.c DMA Tasks
31 - drivers/dma/MCD_tasksInit.c DMA Tasks Init
32 - drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver
35 - include/MCD_dma.h DMA header file
36 - include/MCD_progCheck.h DMA header file
37 - include/MCD_tasksInit.h DMA header file
43 - include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition
/openbmc/u-boot/drivers/usb/musb-new/
H A DKconfig60 bool "Disable DMA (always use PIO)"
64 DMA controllers are ignored.
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3xmb_cmp.dtsi32 dmas = <0>, <0>; /* Do not use DMA for spi0 */
83 dmas = <0>, <0>; /* Do not use DMA for usart1 */
181 dmas = <0>, <0>; /* Do not use DMA for dbgu */
H A Dsama5d3xmb.dtsi34 dmas = <0>, <0>; /* Do not use DMA for spi0 */
87 dmas = <0>, <0>; /* Do not use DMA for usart1 */
184 dmas = <0>, <0>; /* Do not use DMA for dbgu */
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dspl_a10.c46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device()
H A Dspl_gen5.c46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device()
/openbmc/u-boot/lib/efi_loader/
H A DKconfig30 bool "EFI Applications use bounce buffers for DMA operations"
34 Some hardware does not support DMA to full 64bit addresses. For this
/openbmc/pldm/oem/ibm/libpldmresponder/
H A Dfile_io_by_type.cpp37 dma::DMA xdmaInterface; in transferFileData()
58 dma::DMA xdmaInterface; in transferFileDataToSocket()
H A Dfile_io.cpp50 int DMA::transferHostDataToSocket(int fd, uint32_t length, uint64_t address) in transferHostDataToSocket()
122 int DMA::transferDataHost(int fd, uint32_t offset, uint32_t length, in transferDataHost()
441 DMA intf; in readFileIntoMemory()
442 return transferAll<DMA>(&intf, PLDM_READ_FILE_INTO_MEMORY, value.fsPath, in readFileIntoMemory()
537 DMA intf; in writeFileFromMemory()
538 return transferAll<DMA>(&intf, PLDM_WRITE_FILE_FROM_MEMORY, value.fsPath, in writeFileFromMemory()
/openbmc/u-boot/include/
H A Ddma.h165 # if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DMA)
/openbmc/qemu/docs/system/arm/
H A Draspi.rst23 * DMA controller
H A Dxlnx-zynq.rst26 - Arm PrimeCell DMA Controller
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c123 MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32); in mctl_set_master_priority_h3()
148 MBUS_CONF( DMA, true, HIGH, 0, 256, 80, 100); in mctl_set_master_priority_a64()
178 MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32); in mctl_set_master_priority_h5()
206 MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32); in mctl_set_master_priority_r40()

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