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Searched refs:DISPLAY_VER (Results 1 – 25 of 75) sorted by relevance

123

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.h35 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
38 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
45 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
46 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
52 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
53 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
56 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
61 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
65 #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
66 #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
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H A Di9xx_plane.c211 if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_plane_ctl()
250 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_check_plane_surface()
364 if (DISPLAY_VER(dev_priv) < 5) in i9xx_plane_ctl_crtc()
427 if (DISPLAY_VER(dev_priv) < 4) { in i9xx_plane_update_noarm()
459 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_update_arm()
494 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_update_arm()
537 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_disable_arm()
685 if (DISPLAY_VER(dev_priv) >= 5) in i9xx_plane_get_hw_state()
834 if (DISPLAY_VER(dev_priv) >= 4) in intel_primary_plane_create()
849 if (DISPLAY_VER(dev_priv) >= 4) in intel_primary_plane_create()
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H A Dintel_fbc.c162 if (DISPLAY_VER(i915) >= 11) in skl_fbc_min_cfb_stride()
186 if (DISPLAY_VER(i915) >= 9) in intel_fbc_cfb_stride()
197 if (DISPLAY_VER(i915) == 7) in intel_fbc_cfb_size()
236 if (DISPLAY_VER(i915) == 2) in i8xx_fbc_ctl()
299 if (DISPLAY_VER(i915) == 4) { in i8xx_fbc_activate()
405 if (DISPLAY_VER(i915) < 6) in g4x_dpfc_ctl()
606 if (DISPLAY_VER(i915) >= 10) in ivb_fbc_activate()
865 if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3) in stride_is_valid()
894 if (DISPLAY_VER(i915) == 2) in pixel_format_is_valid()
1145 if (DISPLAY_VER(i915) >= 9 && in intel_fbc_check_plane()
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H A Dintel_wm.c165 if (DISPLAY_VER(dev_priv) >= 9) in intel_print_wm_latency()
178 if (DISPLAY_VER(i915) >= 9) in intel_wm_init()
198 if (DISPLAY_VER(dev_priv) >= 9 || in wm_latency_show()
218 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_show()
233 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_show()
248 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_show()
262 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in pri_wm_latency_open()
329 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_write()
344 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_write()
359 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_write()
H A Dintel_psr.c240 if (DISPLAY_VER(dev_priv) >= 8) in psr_ctl_reg()
249 if (DISPLAY_VER(dev_priv) >= 8) in psr_debug_reg()
258 if (DISPLAY_VER(dev_priv) >= 8) in psr_perf_cnt_reg()
267 if (DISPLAY_VER(dev_priv) >= 8) in psr_status_reg()
276 if (DISPLAY_VER(dev_priv) >= 12) in psr_imr_reg()
285 if (DISPLAY_VER(dev_priv) >= 12) in psr_iir_reg()
294 if (DISPLAY_VER(dev_priv) >= 8) in psr_aux_ctl_reg()
303 if (DISPLAY_VER(dev_priv) >= 8) in psr_aux_data_reg()
739 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) in hsw_activate_psr2()
1034 if (DISPLAY_VER(i915) >= 12) { in _compute_psr2_wake_times()
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H A Dintel_display_irq.c187 if (DISPLAY_VER(dev_priv) < 5) in i915_pipestat_enable_mask()
289 if (DISPLAY_VER(dev_priv) >= 4) in i915_enable_asle_pipestat()
381 if (DISPLAY_VER(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
795 if (DISPLAY_VER(dev_priv) >= 14) in gen8_de_port_aux_mask()
820 if (DISPLAY_VER(dev_priv) >= 9) in gen8_de_port_aux_mask()
891 if (DISPLAY_VER(dev_priv) < 12) in gen8_de_misc_irq_handler()
958 if (DISPLAY_VER(i915) >= 9) in gen8_de_pipe_flip_done_mask()
968 if (DISPLAY_VER(dev_priv) >= 13) in gen8_de_pipe_underrun_mask()
1474 if (DISPLAY_VER(dev_priv) >= 14) in gen11_display_irq_reset()
1647 if (DISPLAY_VER(dev_priv) >= 14) in gen8_de_irq_postinstall()
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H A Dskl_universal_plane.c473 if (DISPLAY_VER(i915) >= 13) { in skl_plane_max_stride()
886 if (DISPLAY_VER(dev_priv) >= 10) in skl_plane_ctl_crtc()
925 if (DISPLAY_VER(dev_priv) >= 11) in skl_plane_ctl()
935 if (DISPLAY_VER(dev_priv) == 13) in skl_plane_ctl()
946 if (DISPLAY_VER(dev_priv) >= 11) in glk_plane_color_ctl_crtc()
1046 if (DISPLAY_VER(i915) < 12) in skl_plane_aux_dist()
1752 if (DISPLAY_VER(i915) >= 13) in skl_check_nv12_aux_surface()
2181 if (DISPLAY_VER(i915) >= 11) in skl_plane_has_rc_ccs()
2195 if (DISPLAY_VER(i915) < 12) in gen12_plane_has_mc_ccs()
2221 if (DISPLAY_VER(i915) < 12) in skl_get_plane_caps()
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H A Dintel_bw.c153 if (DISPLAY_VER(dev_priv) >= 14) in icl_pcode_restrict_qgv_points()
202 if (DISPLAY_VER(dev_priv) >= 14) in intel_read_qgv_point_info()
220 if (DISPLAY_VER(dev_priv) >= 14) { in icl_get_qgv_points()
666 if (DISPLAY_VER(dev_priv) >= 14) in intel_bw_init_hw()
708 if (DISPLAY_VER(i915) < 11) in intel_bw_crtc_data_rate()
721 if (DISPLAY_VER(i915) < 12) in intel_bw_crtc_min_cdclk()
900 if (DISPLAY_VER(i915) > 11) in icl_find_qgv_points()
1002 if (DISPLAY_VER(i915) >= 14) in intel_bw_check_qgv_points()
1082 if (DISPLAY_VER(i915) < 11) in skl_crtc_calc_dbuf_bw()
1146 if (DISPLAY_VER(dev_priv) < 9) in intel_bw_calc_min_cdclk()
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H A Dintel_fifo_underrun.c196 if (DISPLAY_VER(dev_priv) >= 13) in icl_pipe_status_underrun_mask()
211 if (DISPLAY_VER(dev_priv) >= 11) in bdw_set_fifo_underrun_reporting()
297 else if (DISPLAY_VER(dev_priv) == 7) in __intel_set_cpu_fifo_underrun_reporting()
299 else if (DISPLAY_VER(dev_priv) >= 8) in __intel_set_cpu_fifo_underrun_reporting()
420 if (DISPLAY_VER(dev_priv) >= 11) { in intel_cpu_fifo_underrun_irq_handler()
429 if (DISPLAY_VER(dev_priv) >= 11) in intel_cpu_fifo_underrun_irq_handler()
484 else if (DISPLAY_VER(dev_priv) == 7) in intel_check_cpu_fifo_underruns()
H A Dintel_ddi.c209 if (DISPLAY_VER(dev_priv) < 10) { in intel_wait_ddi_buf_active()
214 if (DISPLAY_VER(dev_priv) >= 14) { in intel_wait_ddi_buf_active()
227 if (DISPLAY_VER(dev_priv) >= 14) in intel_wait_ddi_buf_active()
337 if (DISPLAY_VER(i915) >= 14) { in intel_ddi_init_dp_buf_reg()
484 if (DISPLAY_VER(dev_priv) >= 12) in intel_ddi_transcoder_func_reg_val_get()
636 if (DISPLAY_VER(dev_priv) >= 11) in intel_ddi_disable_transcoder_func()
989 if (DISPLAY_VER(dev_priv) >= 13) in intel_ddi_enable_transcoder_clock()
4145 if (DISPLAY_VER(dev_priv) < 9) in intel_ddi_port_sync_transcoders()
4265 if (DISPLAY_VER(i915) >= 14) in intel_ddi_init_dp_connector()
4625 if (DISPLAY_VER(i915) >= 12) in intel_ddi_is_tc()
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H A Dintel_sprite_uapi.c13 return DISPLAY_VER(dev_priv) >= 9; in has_dst_key_in_primary_plane()
37 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && in intel_plane_set_ckey()
76 if (DISPLAY_VER(dev_priv) >= 9 && in intel_sprite_set_colorkey_ioctl()
H A Dintel_vrr.c81 if (DISPLAY_VER(i915) >= 13) in intel_vrr_vblank_exit_length()
149 if (DISPLAY_VER(i915) >= 13) { in intel_vrr_compute_config()
168 if (DISPLAY_VER(i915) >= 13) in trans_vrr_ctl()
186 if (DISPLAY_VER(dev_priv) == 13) in intel_vrr_set_transcoder_timings()
265 if (DISPLAY_VER(dev_priv) >= 13) in intel_vrr_get_config()
H A Dintel_display_power.c969 DISPLAY_VER(dev_priv) >= 11 ? in get_allowed_dc_mask()
1117 if (DISPLAY_VER(dev_priv) >= 14) in gen9_dbuf_enable()
1131 if (DISPLAY_VER(dev_priv) >= 14) in gen9_dbuf_disable()
1170 if (DISPLAY_VER(dev_priv) == 12) in icl_mbus_init()
1430 if (DISPLAY_VER(dev_priv) >= 14) in intel_pch_reset_handshake()
1675 if (DISPLAY_VER(dev_priv) == 14) in icl_display_core_init()
1920 if (DISPLAY_VER(i915) >= 11) { in intel_power_domains_init_hw()
2108 if (DISPLAY_VER(i915) >= 11) in intel_power_domains_suspend()
2265 if (DISPLAY_VER(i915) >= 11) { in intel_display_power_suspend()
2280 if (DISPLAY_VER(i915) >= 11) { in intel_display_power_resume()
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H A Dintel_crtc.c114 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in intel_crtc_max_vblank_count()
116 else if (DISPLAY_VER(dev_priv) >= 3) in intel_crtc_max_vblank_count()
311 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
327 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
350 else if (DISPLAY_VER(dev_priv) == 4) in intel_crtc_init()
354 else if (DISPLAY_VER(dev_priv) == 3) in intel_crtc_init()
359 if (DISPLAY_VER(dev_priv) >= 8) in intel_crtc_init()
371 if (DISPLAY_VER(dev_priv) >= 11) in intel_crtc_init()
691 if (DISPLAY_VER(dev_priv) >= 11 && in intel_pipe_update_end()
H A Dskl_watermark.c63 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
76 if (DISPLAY_VER(i915) >= 14) { in intel_sagv_block_time()
113 if (DISPLAY_VER(i915) < 11) in intel_sagv_init()
312 if (DISPLAY_VER(i915) >= 11) in intel_sagv_pre_plane_update()
332 if (DISPLAY_VER(i915) >= 11) in intel_sagv_post_plane_update()
418 if (DISPLAY_VER(i915) >= 12) in intel_crtc_can_enable_sagv()
427 if (DISPLAY_VER(i915) < 11 && in intel_can_enable_sagv()
492 DISPLAY_VER(i915) >= 12 && in intel_compute_sagv_mask()
793 if (DISPLAY_VER(i915) >= 11) in skl_ddb_get_hw_plane_state()
2039 if (DISPLAY_VER(i915) == 9) in skl_compute_transition_wm()
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H A Dintel_display.c291 if (DISPLAY_VER(dev_priv) >= 4) { in intel_wait_for_pipe_off()
427 if (DISPLAY_VER(dev_priv) == 13) in intel_enable_transcoder()
486 if (DISPLAY_VER(dev_priv) >= 14) in intel_disable_transcoder()
840 if (DISPLAY_VER(dev_priv) == 9) in needs_nv12_wa()
873 if (DISPLAY_VER(i915) == 9) { in intel_async_flip_vtd_wa()
1601 if (DISPLAY_VER(dev_priv) < 9) in hsw_crtc_enable()
2304 if (DISPLAY_VER(i915) < 4) { in intel_crtc_compute_pipe_mode()
2538 if (DISPLAY_VER(dev_priv) > 3) in intel_set_transcoder_timings()
3374 if (DISPLAY_VER(i915) >= 12) in bigjoiner_pipes()
3481 if (DISPLAY_VER(i915) >= 11) in hsw_panel_transcoders()
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H A Dskl_scaler.c133 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable && in skl_update_scaler()
177 if (DISPLAY_VER(dev_priv) < 11) { in skl_update_scaler()
182 } else if (DISPLAY_VER(dev_priv) < 12) { in skl_update_scaler()
187 } else if (DISPLAY_VER(dev_priv) < 14) { in skl_update_scaler()
337 if (DISPLAY_VER(dev_priv) >= 11) in skl_update_scaler_plane()
383 if (DISPLAY_VER(dev_priv) == 9) { in intel_atomic_setup_scaler()
401 } else if (DISPLAY_VER(dev_priv) >= 10) { in intel_atomic_setup_scaler()
435 if (DISPLAY_VER(dev_priv) >= 14) { in intel_atomic_setup_scaler()
448 } else if (DISPLAY_VER(dev_priv) >= 10 || in intel_atomic_setup_scaler()
572 if (DISPLAY_VER(dev_priv) >= 10) in intel_atomic_setup_scalers()
H A Dintel_dp_aux.c204 if (DISPLAY_VER(i915) >= 14) in skl_get_aux_send_ctl()
732 if (DISPLAY_VER(dev_priv) >= 14) { in intel_dp_aux_init()
735 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_dp_aux_init()
738 } else if (DISPLAY_VER(dev_priv) >= 9) { in intel_dp_aux_init()
749 if (DISPLAY_VER(dev_priv) >= 9) in intel_dp_aux_init()
758 if (DISPLAY_VER(dev_priv) >= 9) in intel_dp_aux_init()
767 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) in intel_dp_aux_init()
771 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) in intel_dp_aux_init()
789 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) in default_aux_ch()
H A Dintel_dp_mst.c197 if (DISPLAY_VER(i915) >= 12) in intel_dp_dsc_mst_compute_link_config()
409 if (DISPLAY_VER(dev_priv) < 12) in intel_dp_mst_transcoder_mask()
461 if (DISPLAY_VER(dev_priv) < 12) in intel_dp_mst_atomic_master_trans_check()
596 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && in intel_mst_post_disable_dp()
612 if (DISPLAY_VER(dev_priv) >= 9) in intel_mst_post_disable_dp()
638 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) in intel_mst_post_disable_dp()
709 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && in intel_mst_pre_enable_dp()
739 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) in intel_mst_pre_enable_dp()
998 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) { in intel_dp_mst_mode_valid_ctx()
1249 if (DISPLAY_VER(i915) < 12 && port == PORT_A) in intel_dp_mst_encoder_init()
[all …]
H A Dintel_pipe_crc.c405 if (DISPLAY_VER(dev_priv) == 2) in get_new_crc_ctl_reg()
407 else if (DISPLAY_VER(dev_priv) < 5) in get_new_crc_ctl_reg()
413 else if (DISPLAY_VER(dev_priv) < 9) in get_new_crc_ctl_reg()
535 if (DISPLAY_VER(dev_priv) == 2) in intel_is_valid_crc_source()
537 else if (DISPLAY_VER(dev_priv) < 5) in intel_is_valid_crc_source()
543 else if (DISPLAY_VER(dev_priv) < 9) in intel_is_valid_crc_source()
H A Dintel_cdclk.c1517 if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1534 if (DISPLAY_VER(dev_priv) >= 12) in bxt_get_cdclk()
1676 if (DISPLAY_VER(dev_priv) >= 12) { in bxt_cdclk_cd2x_pipe()
1943 if (DISPLAY_VER(dev_priv) >= 14) in bxt_set_cdclk()
1951 if (DISPLAY_VER(dev_priv) < 11) { in bxt_set_cdclk()
1972 if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
2099 else if (DISPLAY_VER(i915) == 9) in intel_cdclk_init_hw()
2114 else if (DISPLAY_VER(i915) == 9) in intel_cdclk_uninit_hw()
2527 if (DISPLAY_VER(dev_priv) >= 10) in intel_pixel_rate_to_cdclk()
2577 if (DISPLAY_VER(dev_priv) == 10) { in intel_crtc_compute_min_cdclk()
[all …]
H A Dintel_dmc.c368 if (DISPLAY_VER(i915) == 12) { in get_flip_queue_event_regs()
414 if (DISPLAY_VER(i915) < 12) in disable_all_event_handlers()
464 if (DISPLAY_VER(i915) >= 14 && enable) in pipedmc_clock_gating_wa()
466 else if (DISPLAY_VER(i915) == 13) in pipedmc_clock_gating_wa()
477 if (DISPLAY_VER(i915) >= 14) in intel_dmc_enable_pipe()
490 if (DISPLAY_VER(i915) >= 14) in intel_dmc_disable_pipe()
690 } else if (DISPLAY_VER(i915) >= 13) { in dmc_mmio_addr_sanity_check()
693 } else if (DISPLAY_VER(i915) >= 12) { in dmc_mmio_addr_sanity_check()
1061 } else if (DISPLAY_VER(i915) == 11) { in intel_dmc_init()
1216 DISPLAY_VER(i915) >= 14)); in intel_dmc_debugfs_status_show()
[all …]
H A Dintel_pmdemand.c116 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_update_phys_mask()
137 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_update_port_clock()
314 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_atomic_check()
389 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_init_pmdemand_params()
585 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_pre_plane_update()
608 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_post_plane_update()
H A Dintel_display_device.c892 else if (DISPLAY_VER(i915) >= 11) { in intel_display_device_info_runtime_init()
895 } else if (DISPLAY_VER(i915) >= 9) { in intel_display_device_info_runtime_init()
901 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) in intel_display_device_info_runtime_init()
904 else if (DISPLAY_VER(i915) >= 11) in intel_display_device_info_runtime_init()
907 else if (DISPLAY_VER(i915) == 10) in intel_display_device_info_runtime_init()
926 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { in intel_display_device_info_runtime_init()
931 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && in intel_display_device_info_runtime_init()
962 } else if (DISPLAY_VER(i915) >= 9) { in intel_display_device_info_runtime_init()
979 if (DISPLAY_VER(i915) >= 12 && in intel_display_device_info_runtime_init()
994 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) in intel_display_device_info_runtime_init()
H A Dintel_audio.c491 if (DISPLAY_VER(i915) < 11) in enable_audio_dsc_wa()
496 if (DISPLAY_VER(i915) == 11) in enable_audio_dsc_wa()
498 else if (DISPLAY_VER(i915) >= 12) in enable_audio_dsc_wa()
872 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) in intel_audio_hooks_init()
883 if (DISPLAY_VER(i915) >= 13) in intel_audio_cdclk_change_pre()
897 if (DISPLAY_VER(i915) >= 13) { in intel_audio_cdclk_change_post()
975 if (DISPLAY_VER(i915) >= 9) { in i915_audio_component_get_power()
987 if (DISPLAY_VER(i915) >= 10) in i915_audio_component_get_power()
1014 if (DISPLAY_VER(i915) < 9) in i915_audio_component_codec_wake_override()
1255 if (DISPLAY_VER(i915) >= 9) { in i915_audio_component_init()
[all …]

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