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Searched refs:DEFINE_PROP_PCIE_LINK_WIDTH (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/pci-bridge/
H A Dgen_pcie_root_port.c146 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
H A Dcxl_downstream.c218 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
H A Dcxl_root_port.c212 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
H A Dcxl_upstream.c370 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort,
/openbmc/qemu/include/hw/
H A Dqdev-properties-system.h78 #define DEFINE_PROP_PCIE_LINK_WIDTH(_n, _s, _f, _d) \ macro
/openbmc/qemu/hw/mem/
H A Dcxl_type3.c1235 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLType3Dev,