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Searched refs:DDR3L (Results 1 – 25 of 28) sorted by relevance

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/openbmc/u-boot/board/freescale/ls1012ardb/
H A DREADME6 optimized to support the high-bandwidth DDR3L memory and
21 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
62 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
/openbmc/u-boot/arch/mips/mach-mscc/
H A DKconfig69 bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)"
78 bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)"
/openbmc/u-boot/board/freescale/ls1012aqds/
H A DREADME6 optimized to support the high-bandwidth DDR3L memory and
21 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A DREADME6 high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
18 - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
88 - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
90 - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
124 - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
214 $ make T1024QDS_defconfig (For DDR3L, by default)
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.cfg34 * DDR3/DDR3L settings
36 * 4x256Mx16 DDR3L-1066 7-7-7
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h45 DDR3L enumerator
/openbmc/u-boot/board/freescale/ls1021aiot/
H A DREADME9 - Supports 1GB un-buffered DDR3L SDRAM discrete
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME21 CAN controller for implementing industrial protocols, DDR3L/4 running
36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME21 CAN controller for implementing industrial protocols, DDR3L/4 running
36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-ddr3l-evk.dts10 model = "NXP i.MX8MNano DDR3L EVK board";
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dimximage.cfg47 /* DDR3L */
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drenesas,raa215300.yaml14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml18 for DDR3L and LPDDR3 SDRAMs.
H A Dnvidia,tegra30-mc.yaml34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp15-ddr3-2x4Gb-1066-binG.dtsi7 * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
H A Dsun50i-a64-pine64.dts194 * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
H A Dsun50i-a64-olinuxino.dts218 * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
/openbmc/u-boot/board/intel/
H A DKconfig15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-pine64.dts191 * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
H A Dsun50i-a64-olinuxino.dts260 * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
82 - Supports 64-bit 4GB DDR3L DIMM
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
136 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME48 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving

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