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Searched refs:CPURISCVState (Results 1 – 25 of 39) sorted by relevance

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/openbmc/qemu/target/riscv/
H A Dfpu_helper.c27 target_ulong riscv_cpu_get_fflags(CPURISCVState *env) in riscv_cpu_get_fflags()
41 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) in riscv_cpu_set_fflags()
54 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode()
280 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) in helper_fsqrt_s()
371 uint64_t helper_fround_s(CPURISCVState *env, uint64_t rs1) in helper_fround_s()
439 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) in helper_fcvt_s_d()
444 uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) in helper_fcvt_d_s()
450 uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) in helper_fsqrt_d()
613 uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) in helper_fsqrt_h()
660 uint64_t helper_fround_h(CPURISCVState *env, uint64_t rs1) in helper_fround_h()
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H A Dpmp.h66 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
68 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
70 void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
71 target_ulong mseccfg_csr_read(CPURISCVState *env);
73 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
76 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
80 target_ulong pmp_get_tlb_size(CPURISCVState *env, target_ulong addr);
81 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
82 void pmp_update_rule_nums(CPURISCVState *env);
83 uint32_t pmp_get_num_rules(CPURISCVState *env);
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H A Dcpu.h35 typedef struct CPUArchState CPURISCVState; typedef
426 CPURISCVState env;
476 uint64_t riscv_cpu_all_pending(CPURISCVState *env);
477 int riscv_cpu_mirq_pending(CPURISCVState *env);
478 int riscv_cpu_sirq_pending(CPURISCVState *env);
479 int riscv_cpu_vsirq_pending(CPURISCVState *env);
480 bool riscv_cpu_fp_enabled(CPURISCVState *env);
483 bool riscv_cpu_vector_enabled(CPURISCVState *env);
510 void riscv_cpu_interrupt(CPURISCVState *env);
637 static inline int riscv_cpu_xlen(CPURISCVState *env) in riscv_cpu_xlen()
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H A Dcsr.c79 static RISCVException fs(CPURISCVState *env, int csrno) in fs()
94 static RISCVException vs(CPURISCVState *env, int csrno) in vs()
107 static RISCVException ctr(CPURISCVState *env, int csrno) in ctr()
227 static RISCVException any(CPURISCVState *env, int csrno) in any()
242 static int aia_any(CPURISCVState *env, int csrno) in aia_any()
251 static int aia_any32(CPURISCVState *env, int csrno) in aia_any32()
269 static int smode32(CPURISCVState *env, int csrno) in smode32()
278 static int aia_smode(CPURISCVState *env, int csrno) in aia_smode()
287 static int aia_smode32(CPURISCVState *env, int csrno) in aia_smode32()
496 static int aia_hmode(CPURISCVState *env, int csrno) in aia_hmode()
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H A Ddebug.h132 bool tdata_available(CPURISCVState *env, int tdata_index);
134 target_ulong tselect_csr_read(CPURISCVState *env);
135 void tselect_csr_write(CPURISCVState *env, target_ulong val);
137 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
138 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
140 target_ulong tinfo_csr_read(CPURISCVState *env);
146 void riscv_trigger_realize(CPURISCVState *env);
147 void riscv_trigger_reset_hold(CPURISCVState *env);
149 bool riscv_itrigger_enabled(CPURISCVState *env);
150 void riscv_itrigger_update_priv(CPURISCVState *env);
H A Ddebug.c166 target_ulong tselect_csr_read(CPURISCVState *env) in tselect_csr_read()
503 itrigger_get_count(CPURISCVState *env, int index) in itrigger_get_count()
530 bool riscv_itrigger_enabled(CPURISCVState *env) in riscv_itrigger_enabled()
550 void helper_itrigger_match(CPURISCVState *env) in helper_itrigger_match()
623 void riscv_itrigger_update_priv(CPURISCVState *env) in riscv_itrigger_update_priv()
751 target_ulong tinfo_csr_read(CPURISCVState *env) in tinfo_csr_read()
761 CPURISCVState *env = &cpu->env; in riscv_cpu_debug_excp_handler()
777 CPURISCVState *env = &cpu->env; in riscv_cpu_debug_check_breakpoint()
836 CPURISCVState *env = &cpu->env; in riscv_cpu_debug_check_watchpoint()
906 void riscv_trigger_realize(CPURISCVState *env) in riscv_trigger_realize()
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H A Dop_helper.c42 target_ulong helper_csrr(CPURISCVState *env, int csr) in helper_csrr()
72 target_ulong helper_csrrw(CPURISCVState *env, int csr, in helper_csrrw()
99 void helper_csrw_i128(CPURISCVState *env, int csr, in helper_csrw_i128()
203 static void check_zicbom_access(CPURISCVState *env, in check_zicbom_access()
264 target_ulong helper_sret(CPURISCVState *env) in helper_sret()
319 target_ulong helper_mret(CPURISCVState *env) in helper_mret()
363 void helper_wfi(CPURISCVState *env) in helper_wfi()
383 void helper_tlb_flush(CPURISCVState *env) in helper_tlb_flush()
398 void helper_tlb_flush_all(CPURISCVState *env) in helper_tlb_flush_all()
404 void helper_hyp_tlb_flush(CPURISCVState *env) in helper_hyp_tlb_flush()
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H A Dpmp.c29 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
31 static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
67 uint32_t pmp_get_num_rules(CPURISCVState *env) in pmp_get_num_rules()
143 void pmp_unlock_entries(CPURISCVState *env) in pmp_unlock_entries()
171 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) in pmp_update_rule_addr()
216 void pmp_update_rule_nums(CPURISCVState *env) in pmp_update_rule_nums()
230 static int pmp_is_in_range(CPURISCVState *env, int pmp_index, in pmp_is_in_range()
308 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, in pmp_hart_has_privs()
467 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, in pmpcfg_csr_write()
576 void mseccfg_csr_write(CPURISCVState *env, target_ulong val) in mseccfg_csr_write()
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H A Dgdbstub.c53 CPURISCVState *env = &cpu->env; in riscv_cpu_gdb_read_register()
79 CPURISCVState *env = &cpu->env; in riscv_cpu_gdb_write_register()
109 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) in riscv_gdb_get_fpu()
122 static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) in riscv_gdb_set_fpu()
131 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) in riscv_gdb_get_vector()
147 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) in riscv_gdb_set_vector()
161 static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) in riscv_gdb_get_csr()
175 static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) in riscv_gdb_set_csr()
189 static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) in riscv_gdb_get_virtual()
218 CPURISCVState *env = &cpu->env; in riscv_gen_dynamic_csr_xml()
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H A Dpmu.h22 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
24 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
28 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
32 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
H A Dinternals.h87 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) in nanbox_s()
97 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) in check_nanbox_s()
113 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) in nanbox_h()
123 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) in check_nanbox_h()
H A Dcommon-semi-target.h17 CPURISCVState *env = &cpu->env; in common_semi_arg()
24 CPURISCVState *env = &cpu->env; in common_semi_set_ret()
41 CPURISCVState *env = &cpu->env; in common_semi_stack_bottom()
H A Dpmu.c93 CPURISCVState *env = &cpu->env; in riscv_pmu_counter_enabled()
105 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr_rv32()
146 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr_rv64()
183 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr()
210 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, in riscv_pmu_ctr_monitor_instructions()
237 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) in riscv_pmu_ctr_monitor_cycles()
284 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, in riscv_pmu_update_event_map()
332 CPURISCVState *env = &cpu->env; in pmu_timer_trigger_irq()
385 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) in riscv_pmu_setup_timer()
H A Dcpu_helper.c148 void riscv_cpu_update_mask(CPURISCVState *env) in riscv_cpu_update_mask()
393 int riscv_cpu_mirq_pending(CPURISCVState *env) in riscv_cpu_mirq_pending()
497 CPURISCVState *env = &cpu->env; in riscv_cpu_exec_interrupt()
509 bool riscv_cpu_fp_enabled(CPURISCVState *env) in riscv_cpu_fp_enabled()
644 CPURISCVState *env = &cpu->env; in riscv_cpu_claim_interrupts()
653 void riscv_cpu_interrupt(CPURISCVState *env) in riscv_cpu_interrupt()
1200 CPURISCVState *env = &cpu->env; in riscv_cpu_get_phys_page_debug()
1227 CPURISCVState *env = &cpu->env; in riscv_cpu_do_transaction_failed()
1248 CPURISCVState *env = &cpu->env; in riscv_cpu_do_unaligned_access()
1295 CPURISCVState *env = &cpu->env; in riscv_cpu_tlb_fill()
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H A Dtranslate.c248 offsetof(CPURISCVState, bins)); in gen_exception_illegal()
258 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); in gen_exception_inst_addr_mis()
633 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_fs_dirty()
635 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_fs_dirty()
662 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_vs_dirty()
1077 CPURISCVState *env = cpu_env(cpu); in opcode_at()
1169 CPURISCVState *env = cpu_env(cs); in riscv_tr_init_disas_context()
1222 CPURISCVState *env = cpu_env(cpu); in riscv_tr_translate_insn()
1268 CPURISCVState *env = &rvcpu->env; in riscv_tr_disas_log()
1310 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); in riscv_translate_init()
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H A Dm128_helper.c25 target_ulong HELPER(divu_i128)(CPURISCVState *env, in HELPER()
45 target_ulong HELPER(remu_i128)(CPURISCVState *env, in HELPER()
65 target_ulong HELPER(divs_i128)(CPURISCVState *env, in HELPER()
90 target_ulong HELPER(rems_i128)(CPURISCVState *env, in HELPER()
H A Dvector_internals.h107 static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, in vext_get_total_elems()
145 CPURISCVState *env, uint32_t desc) \
182 CPURISCVState *env, uint32_t desc,
188 void *vs2, CPURISCVState *env, \
209 CPURISCVState *env, uint32_t desc,
215 void *vs2, CPURISCVState *env, \
H A Dtime_helper.c28 CPURISCVState *env = &cpu->env; in riscv_vstimer_cb()
43 void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, in riscv_timer_write_timecmp()
129 CPURISCVState *env; in riscv_timer_init()
H A Dmachine.c37 CPURISCVState *env = &cpu->env; in pmp_post_load()
75 CPURISCVState *env = &cpu->env; in hyper_needed()
131 CPURISCVState *env = &cpu->env; in vector_needed()
156 CPURISCVState *env = &cpu->env; in pointermasking_needed()
182 CPURISCVState *env = &cpu->env; in rv128_needed()
209 CPURISCVState *env = &cpu->env; in cpu_kvmtimer_post_load()
240 CPURISCVState *env = &cpu->env; in debug_post_load()
267 CPURISCVState *env = &cpu->env; in riscv_cpu_post_load()
297 CPURISCVState *env = &cpu->env; in envcfg_needed()
H A Dvector_helper.c141 static void NAME(CPURISCVState *env, abi_ptr addr, \
188 target_ulong stride, CPURISCVState *env, in vext_ldst_stride()
329 CPURISCVState *env, uint32_t desc)
338 CPURISCVState *env, uint32_t desc) in HELPER()
455 CPURISCVState *env, uint32_t desc,
590 CPURISCVState *env, uint32_t desc) \
615 CPURISCVState *env, uint32_t desc) \ in GEN_VEXT_LD_WHOLE()
1903 CPURISCVState *env, in vext_vv_rm_1()
1920 CPURISCVState *env, in vext_vv_rm_2()
2028 CPURISCVState *env, in vext_vx_rm_1()
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H A Dcpu.c380 CPURISCVState *env = &cpu->env; in riscv_any_cpu_init()
405 CPURISCVState *env = &cpu->env; in riscv_max_cpu_init()
435 CPURISCVState *env = &cpu->env; in rv64_sifive_u_cpu_init()
571 CPURISCVState *env = &cpu->env; in rv32_sifive_u_cpu_init()
669 CPURISCVState *env = &cpu->env; in riscv_cpu_dump_state()
795 CPURISCVState *env = &cpu->env; in riscv_cpu_set_pc()
807 CPURISCVState *env = &cpu->env; in riscv_cpu_get_pc()
820 CPURISCVState *env = &cpu->env; in riscv_cpu_has_work()
842 CPURISCVState *env = &cpu->env; in riscv_cpu_reset_hold()
928 CPURISCVState *env = &cpu->env; in riscv_cpu_disas_set_info()
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/openbmc/qemu/linux-user/riscv/
H A Dtarget_cpu.h4 static inline void cpu_clone_regs_child(CPURISCVState *env, target_ulong newsp, in cpu_clone_regs_child()
14 static inline void cpu_clone_regs_parent(CPURISCVState *env, unsigned flags) in cpu_clone_regs_parent()
18 static inline void cpu_set_tls(CPURISCVState *env, target_ulong newtls) in cpu_set_tls()
23 static inline abi_ulong get_sp_from_cpustate(CPURISCVState *state) in get_sp_from_cpustate()
H A Dsignal.c63 CPURISCVState *regs, size_t framesize) in get_sigframe()
80 static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env) in setup_sigcontext()
98 CPURISCVState *env, target_sigset_t *set) in setup_ucontext()
115 target_sigset_t *set, CPURISCVState *env) in setup_rt_frame()
147 static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc) in restore_sigcontext()
165 static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc) in restore_ucontext()
182 long do_rt_sigreturn(CPURISCVState *env) in do_rt_sigreturn()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c49 CPURISCVState *env = &cpu->env; in riscv_cpu_synchronize_from_tb()
67 CPURISCVState *env = &cpu->env; in riscv_restore_state_to_opc()
120 CPURISCVState *env = &cpu->env; in cpu_cfg_ext_auto_update()
155 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_misa_mxl()
180 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_priv_spec()
246 CPURISCVState *env = &cpu->env; in riscv_cpu_disable_priv_spec_isa_exts()
282 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_set_extensions()
625 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_finalize_features()
692 CPURISCVState *env = &cpu->env; in tcg_cpu_realize()
733 CPURISCVState *env = &cpu->env; in cpu_set_misa_ext_cfg()
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/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c150 CPURISCVState *env = &cpu->env; in kvm_cpu_get_misa_ext_cfg()
163 CPURISCVState *env = &cpu->env; in kvm_cpu_set_misa_ext_cfg()
191 CPURISCVState *env = &cpu->env; in kvm_riscv_update_cpu_misa_ext()
356 CPURISCVState *env = &cpu->env; in kvm_riscv_update_cpu_cfg_isa_ext()
489 CPURISCVState *env = &RISCV_CPU(cs)->env; in kvm_riscv_get_regs_core()
745 CPURISCVState *env = &cpu->env; in kvm_riscv_init_machine_ids()
777 CPURISCVState *env = &cpu->env; in kvm_riscv_init_misa_ext_mask()
799 CPURISCVState *env = &cpu->env; in kvm_riscv_read_cbomz_blksize()
817 CPURISCVState *env = &cpu->env; in kvm_riscv_read_multiext_legacy()
1080 CPURISCVState *env = &cpu->env; in kvm_vcpu_set_machine_ids()
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