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Searched refs:CPURISCVState (Results 1 – 25 of 50) sorted by relevance

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/openbmc/qemu/target/riscv/
H A Dfpu_helper.c27 target_ulong riscv_cpu_get_fflags(CPURISCVState *env) in riscv_cpu_get_fflags()
41 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) in riscv_cpu_set_fflags()
54 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode()
84 void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode_chkfrm()
121 static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_h()
131 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_s()
141 uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, in helper_fmadd_s()
147 uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, in helper_fmadd_d()
153 uint64_t helper_fmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, in helper_fmadd_h()
159 uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, in helper_fmsub_s()
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H A Dcpu.h36 typedef struct CPUArchState CPURISCVState; typedef
500 CPURISCVState env;
531 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) in riscv_has_ext()
551 uint64_t riscv_cpu_all_pending(CPURISCVState *env);
552 int riscv_cpu_mirq_pending(CPURISCVState *env);
553 int riscv_cpu_sirq_pending(CPURISCVState *env);
554 int riscv_cpu_vsirq_pending(CPURISCVState *env);
555 bool riscv_cpu_fp_enabled(CPURISCVState *env);
556 target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
557 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
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H A Dcsr.c46 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) in smstateen_acc_ok()
78 static RISCVException fs(CPURISCVState *env, int csrno) in fs()
93 static RISCVException vs(CPURISCVState *env, int csrno) in vs()
106 static RISCVException ctr(CPURISCVState *env, int csrno) in ctr()
162 static RISCVException ctr32(CPURISCVState *env, int csrno) in ctr32()
171 static RISCVException zcmt(CPURISCVState *env, int csrno) in zcmt()
187 static RISCVException cfi_ss(CPURISCVState *env, int csrno) in cfi_ss()
207 static RISCVException mctr(CPURISCVState *env, int csrno) in mctr()
230 static RISCVException mctr32(CPURISCVState *env, int csrno) in mctr32()
239 static RISCVException sscofpmf(CPURISCVState *env, int csrno) in sscofpmf()
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H A Dpmp.h67 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
69 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
71 void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
72 target_ulong mseccfg_csr_read(CPURISCVState *env);
74 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
76 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
77 bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
81 target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr);
82 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
83 void pmp_update_rule_nums(CPURISCVState *env);
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H A Dop_helper.c29 G_NORETURN void riscv_raise_exception(CPURISCVState *env, in riscv_raise_exception()
37 void helper_raise_exception(CPURISCVState *env, uint32_t exception) in helper_raise_exception()
42 target_ulong helper_csrr(CPURISCVState *env, int csr) in helper_csrr()
62 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) in helper_csrw()
72 target_ulong helper_csrrw(CPURISCVState *env, int csr, in helper_csrrw()
84 target_ulong helper_csrr_i128(CPURISCVState *env, int csr) in helper_csrr_i128()
97 void helper_csrw_i128(CPURISCVState *env, int csr, in helper_csrw_i128()
109 target_ulong helper_csrrw_i128(CPURISCVState *env, int csr, in helper_csrrw_i128()
134 static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits, in check_zicbo_envcfg()
154 void helper_cbo_zero(CPURISCVState *env, target_ulong address) in helper_cbo_zero()
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H A Ddebug.h137 bool tdata_available(CPURISCVState *env, int tdata_index);
139 target_ulong tselect_csr_read(CPURISCVState *env);
140 void tselect_csr_write(CPURISCVState *env, target_ulong val);
142 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
143 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
145 target_ulong tinfo_csr_read(CPURISCVState *env);
151 void riscv_trigger_realize(CPURISCVState *env);
152 void riscv_trigger_reset_hold(CPURISCVState *env);
154 bool riscv_itrigger_enabled(CPURISCVState *env);
155 void riscv_itrigger_update_priv(CPURISCVState *env);
H A Ddebug.c77 static inline target_ulong extract_trigger_type(CPURISCVState *env, in extract_trigger_type()
91 static inline target_ulong get_trigger_type(CPURISCVState *env, in get_trigger_type()
97 static trigger_action_t get_trigger_action(CPURISCVState *env, in get_trigger_action()
130 static inline target_ulong build_tdata1(CPURISCVState *env, in build_tdata1()
155 bool tdata_available(CPURISCVState *env, int tdata_index) in tdata_available()
166 target_ulong tselect_csr_read(CPURISCVState *env) in tselect_csr_read()
171 void tselect_csr_write(CPURISCVState *env, target_ulong val) in tselect_csr_write()
178 static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, in tdata1_validate()
220 static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3) in textra_validate()
280 static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index) in do_trigger_action()
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H A Dpmu.h25 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
27 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
31 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
35 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
37 void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv,
39 RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
H A Dpmp.c30 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
32 static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
46 static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index) in pmp_is_locked()
68 uint32_t pmp_get_num_rules(CPURISCVState *env) in pmp_get_num_rules()
76 static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index) in pmp_read_cfg()
90 static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) in pmp_write_cfg()
144 void pmp_unlock_entries(CPURISCVState *env) in pmp_unlock_entries()
171 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) in pmp_update_rule_addr()
216 void pmp_update_rule_nums(CPURISCVState *env) in pmp_update_rule_nums()
230 static int pmp_is_in_range(CPURISCVState *env, int pmp_index, hwaddr addr) in pmp_is_in_range()
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H A Dgdbstub.c54 CPURISCVState *env = &cpu->env; in riscv_cpu_gdb_read_register()
81 CPURISCVState *env = &cpu->env; in riscv_cpu_gdb_write_register()
114 CPURISCVState *env = &cpu->env; in riscv_gdb_get_fpu()
130 CPURISCVState *env = &cpu->env; in riscv_gdb_set_fpu()
142 CPURISCVState *env = &cpu->env; in riscv_gdb_get_vector()
160 CPURISCVState *env = &cpu->env; in riscv_gdb_set_vector()
176 CPURISCVState *env = &cpu->env; in riscv_gdb_get_csr()
193 CPURISCVState *env = &cpu->env; in riscv_gdb_set_csr()
214 CPURISCVState *env = &cpu->env; in riscv_gdb_get_virtual()
227 CPURISCVState *env = &cpu->env; in riscv_gdb_set_virtual()
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H A Dpmu.c94 CPURISCVState *env = &cpu->env; in riscv_pmu_counter_enabled()
106 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr_rv32()
147 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr_rv64()
192 static void riscv_pmu_icount_update_priv(CPURISCVState *env, in riscv_pmu_icount_update_priv()
232 static void riscv_pmu_cycle_update_priv(CPURISCVState *env, in riscv_pmu_cycle_update_priv()
268 void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, in riscv_pmu_update_fixed_ctrs()
279 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr()
305 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, in riscv_pmu_ctr_monitor_instructions()
332 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) in riscv_pmu_ctr_monitor_cycles()
379 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, in riscv_pmu_update_event_map()
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H A Dinternals.h90 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) in nanbox_s()
100 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) in check_nanbox_s()
116 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) in nanbox_h()
126 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) in check_nanbox_h()
H A Dcpu_helper.c38 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) in riscv_env_mmu_index()
67 bool cpu_get_fcfien(CPURISCVState *env) in cpu_get_fcfien()
94 bool cpu_get_bcfien(CPURISCVState *env) in cpu_get_bcfien()
123 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, in cpu_get_tb_cpu_state()
223 void riscv_cpu_update_mask(CPURISCVState *env) in riscv_cpu_update_mask()
415 static int riscv_cpu_pending_to_irq(CPURISCVState *env, in riscv_cpu_pending_to_irq()
459 uint64_t riscv_cpu_all_pending(CPURISCVState *env) in riscv_cpu_all_pending()
468 int riscv_cpu_mirq_pending(CPURISCVState *env) in riscv_cpu_mirq_pending()
477 int riscv_cpu_sirq_pending(CPURISCVState *env) in riscv_cpu_sirq_pending()
487 int riscv_cpu_vsirq_pending(CPURISCVState *env) in riscv_cpu_vsirq_pending()
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H A Dcommon-semi-target.h17 CPURISCVState *env = &cpu->env; in common_semi_arg()
24 CPURISCVState *env = &cpu->env; in common_semi_set_ret()
41 CPURISCVState *env = &cpu->env; in common_semi_stack_bottom()
H A Dm128_helper.c25 target_ulong HELPER(divu_i128)(CPURISCVState *env, in HELPER()
45 target_ulong HELPER(remu_i128)(CPURISCVState *env, in HELPER()
65 target_ulong HELPER(divs_i128)(CPURISCVState *env, in HELPER()
90 target_ulong HELPER(rems_i128)(CPURISCVState *env, in HELPER()
H A Dtranslate.c257 offsetof(CPURISCVState, bins)); in gen_exception_illegal()
267 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); in gen_exception_inst_addr_mis()
642 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_fs_dirty()
644 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_fs_dirty()
647 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); in mark_fs_dirty()
649 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); in mark_fs_dirty()
671 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_vs_dirty()
673 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_vs_dirty()
676 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); in mark_vs_dirty()
678 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); in mark_vs_dirty()
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H A Dvector_internals.h113 static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, in vext_get_total_elems()
151 CPURISCVState *env, uint32_t desc) \
190 CPURISCVState *env, uint32_t desc,
196 void *vs2, CPURISCVState *env, \
217 CPURISCVState *env, uint32_t desc,
223 void *vs2, CPURISCVState *env, \
H A Dtime_helper.c28 CPURISCVState *env = &cpu->env; in riscv_vstimer_cb()
43 void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, in riscv_timer_write_timecmp()
130 CPURISCVState *env; in riscv_timer_init()
H A Dvector_helper.c34 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, in HELPER()
108 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) in adjust_addr()
123 static void probe_pages(CPURISCVState *env, target_ulong addr, in probe_pages()
151 typedef void vext_ldst_elem_fn_tlb(CPURISCVState *env, abi_ptr addr,
157 void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \
178 void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ in GEN_VEXT_LD_ELEM()
198 vext_continus_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb,
210 vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host, in vext_continus_ldst_host()
258 CPURISCVState *env, uint32_t desc, uint32_t vm, in vext_ldst_stride()
292 target_ulong stride, CPURISCVState *env, \
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H A Dmachine.c37 CPURISCVState *env = &cpu->env; in pmp_post_load()
75 CPURISCVState *env = &cpu->env; in hyper_needed()
131 CPURISCVState *env = &cpu->env; in vector_needed()
156 CPURISCVState *env = &cpu->env; in pointermasking_needed()
208 CPURISCVState *env = &cpu->env; in cpu_kvmtimer_post_load()
239 CPURISCVState *env = &cpu->env; in debug_post_load()
266 CPURISCVState *env = &cpu->env; in riscv_cpu_post_load()
296 CPURISCVState *env = &cpu->env; in envcfg_needed()
/openbmc/qemu/linux-user/riscv/
H A Dtarget_cpu.h4 static inline void cpu_clone_regs_child(CPURISCVState *env, target_ulong newsp, in cpu_clone_regs_child()
14 static inline void cpu_clone_regs_parent(CPURISCVState *env, unsigned flags) in cpu_clone_regs_parent()
18 static inline void cpu_set_tls(CPURISCVState *env, target_ulong newtls) in cpu_set_tls()
23 static inline abi_ulong get_sp_from_cpustate(CPURISCVState *state) in get_sp_from_cpustate()
H A Dsignal.c63 CPURISCVState *regs, size_t framesize) in get_sigframe()
80 static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env) in setup_sigcontext()
98 CPURISCVState *env, target_sigset_t *set) in setup_ucontext()
115 target_sigset_t *set, CPURISCVState *env) in setup_rt_frame()
147 static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc) in restore_sigcontext()
165 static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc) in restore_ucontext()
182 long do_rt_sigreturn(CPURISCVState *env) in do_rt_sigreturn()
/openbmc/qemu/bsd-user/riscv/
H A Dtarget_arch_vmparam.h38 static inline abi_ulong get_sp_from_cpustate(CPURISCVState *state) in get_sp_from_cpustate()
43 static inline void set_second_rval(CPURISCVState *state, abi_ulong retval2) in set_second_rval()
48 static inline abi_ulong get_second_rval(CPURISCVState *state) in get_second_rval()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzicfiss.c.inc28 tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
35 tcg_env, offsetof(CPURISCVState, sw_check_code));
40 tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
55 tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
59 tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
71 tcg_gen_ld_tl(dest, tcg_env, offsetof(CPURISCVState, ssp));
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c73 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
98 CPURISCVState *env = &cpu->env; in riscv_cpu_synchronize_from_tb()
116 CPURISCVState *env = &cpu->env; in riscv_restore_state_to_opc()
214 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, in cpu_bump_multi_ext_priv_ver()
237 CPURISCVState *env = &cpu->env; in cpu_cfg_ext_auto_update()
260 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) in riscv_cpu_validate_misa_priv()
268 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, in riscv_cpu_validate_v()
290 CPURISCVState *env = &cpu->env; in riscv_cpu_disable_priv_spec_isa_exts()
417 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_set_extensions()
690 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_profile()
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