Searched refs:CP1 (Results 1 – 9 of 9) sorted by relevance
211 * [7] CP1 SPI0 CSn1 (FXS)212 * [8] CP1 SPI0 CSn0 (TPM)213 * [9.11]CP1 SPI0 MOSI/MISO/CLK214 * [13] CP1 SPI1 MISO (TDM and SPI ROM shared)215 * [14] CP1 SPI1 CS0n (64Mb SPI ROM)216 * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)217 * [16] CP1 SPI1 CLK (TDM and SPI ROM shared)220 * [27] CP1 SMI MDIO221 * [28] CP1 SMI MDC266 * CP1 Serdes Configuration:
100 * [62] CP1 SFI SFP FAULT221 * [8] CP1 10G SFP LOS222 * [9] CP1 10G PHY RESET223 * [10] CP1 10G SFP TX Disable224 * [11] CP1 10G SFP Mode230 * [24] CP1 2.5G SFP TX Disable280 * CP1 Serdes Configuration:
247 /* CON6 on CP1 expansion */256 /* CON5 on CP1 expansion */290 /* CON4 on CP1 expansion */295 /* CON9 on CP1 expansion */300 /* CON10 on CP1 expansion */
212 /* CON6 on CP1 expansion */219 /* CON7 on CP1 expansion */226 /* CON5 on CP1 expansion */269 * MDIO signal of CP1.303 /* CON4 on CP1 expansion */321 /* CON9 on CP1 expansion */330 /* CON10 on CP1 expansion */
430 * [7] CP1 SPI0 CSn1 (FXS)431 * [8] CP1 SPI0 CSn0 (TPM)432 * [9.11]CP1 SPI0 MOSI/MISO/CLK433 * [13] CP1 SPI1 MISO (TDM and SPI ROM shared)434 * [14] CP1 SPI1 CS0n (64Mb SPI ROM)435 * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)436 * [16] CP1 SPI1 CLK (TDM and SPI ROM shared)439 * [27] CP1 SMI MDIO440 * [28] CP1 SMI MDC
73 @ CP0 and CP1 accessible?76 @ enable access to CP0 and CP1204 @ enable access to CP0 and CP1215 @ disable access to CP0 and CP1313 @ CP0 and CP1 accessible?
1057 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,1058 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
851 #define CP1 (1 << 1) macro
488 /* P.GP.CP1 instruction pool */2551 /* nanoMIPS CP1 Branches */