Searched refs:CP0_Status (Results 1 – 11 of 11) sorted by relevance
167 return (env->CP0_Status & (1 << CP0St_IE)) && in cpu_mips_hw_interrupts_enabled()168 !(env->CP0_Status & (1 << CP0St_EXL)) && in cpu_mips_hw_interrupts_enabled()169 !(env->CP0_Status & (1 << CP0St_ERL)) && in cpu_mips_hw_interrupts_enabled()187 status = env->CP0_Status & CP0Ca_IP_mask; in cpu_mips_hw_interrupts_pending()307 if (env->CP0_Status & (1 << CP0St_ERL)) { in compute_hflags()310 if (!(env->CP0_Status & (1 << CP0St_EXL)) && in compute_hflags()311 !(env->CP0_Status & (1 << CP0St_ERL)) && in compute_hflags()313 env->hflags |= (env->CP0_Status >> CP0St_KSU) & in compute_hflags()319 (env->CP0_Status & (1 << CP0St_PX)) || in compute_hflags()320 (env->CP0_Status & (1 << CP0St_UX)))) { in compute_hflags()[all …]
40 if (env->CP0_Status & (1 << CP0St_FR)) { in mips_cpu_gdb_read_register()51 return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status); in mips_cpu_gdb_read_register()100 if (env->CP0_Status & (1 << CP0St_FR)) { in mips_cpu_gdb_write_register()
35 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); in msa_reset()
764 int32_t CP0_Status; member
31 target_ulong t0 = env->CP0_Status; in helper_di()33 env->CP0_Status = t0 & ~(1 << CP0St_IE); in helper_di()39 target_ulong t0 = env->CP0_Status; in helper_ei()41 env->CP0_Status = t0 | (1 << CP0St_IE); in helper_ei()50 if (env->CP0_Status & (1 << CP0St_ERL)) { in debug_pre_eret()65 if (env->CP0_Status & (1 << CP0St_ERL)) { in debug_post_eret()107 if (env->CP0_Status & (1 << CP0St_ERL)) { in exception_return()109 env->CP0_Status &= ~(1 << CP0St_ERL); in exception_return()112 env->CP0_Status &= ~(1 << CP0St_EXL); in exception_return()
176 cpu->CP0_Status &= ~mask; in sync_c0_tcstatus()177 cpu->CP0_Status |= status; in sync_c0_tcstatus()395 return other->CP0_Status; in helper_mftc0_status()1121 old = env->CP0_Status; in helper_mtc0_status()1123 val = env->CP0_Status; in helper_mtc0_status()1156 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); in helper_mttc0_status()
13 if (env->CP0_Status & (1 << CP0St_FR)) { in do_prctl_get_fp_mode()25 bool old_fr = env->CP0_Status & (1 << CP0St_FR); in do_prctl_set_fp_mode()68 env->CP0_Status |= (1 << CP0St_FR); in do_prctl_set_fp_mode()71 env->CP0_Status &= ~(1 << CP0St_FR); in do_prctl_set_fp_mode()
30 uint32_t v = cpu->CP0_Status; in sync_c0_status()64 target_ulong old = env->CP0_Status; in cpu_mips_store_status()80 env->CP0_Status = (old & ~mask) | (val & mask); in cpu_mips_store_status()82 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { in cpu_mips_store_status()
124 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; in get_physical_address()125 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; in get_physical_address()126 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; in get_physical_address()183 if (env->CP0_Status & am_ksux[am]) { in get_physical_address()
291 VMSTATE_INT32(env.CP0_Status, MIPSCPU),
52 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); in helper_cfc1()96 env->CP0_Status &= ~(1 << CP0St_FR); in helper_ctc1()108 env->CP0_Status |= (1 << CP0St_FR); in helper_ctc1()