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Searched refs:CP0_Config5 (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/linux-user/mips/
H A Dtarget_prctl.h16 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { in do_prctl_get_fp_mode()
26 bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); in do_prctl_set_fp_mode()
75 env->CP0_Config5 |= (1 << CP0C5_FRE); in do_prctl_set_fp_mode()
80 env->CP0_Config5 &= ~(1 << CP0C5_FRE); in do_prctl_set_fp_mode()
/openbmc/qemu/target/mips/
H A Dinternal.h41 int32_t CP0_Config5; member
351 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { in compute_hflags()
402 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { in compute_hflags()
407 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { in compute_hflags()
H A Dmsa.c34 env->CP0_Config5 |= 1 << CP0C5_MSAEn; in msa_reset()
H A Dcpu-defs.c.inc384 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
409 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
444 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
487 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
528 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
759 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) |
800 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) |
913 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
H A Dcpu.h926 int32_t CP0_Config5; member
/openbmc/qemu/hw/mips/
H A Dcps.c60 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); in cpu_mips_itu_supported()
/openbmc/qemu/target/mips/tcg/
H A Dfpu_helper.c50 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_cfc1()
61 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_cfc1()
62 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1; in helper_cfc1()
95 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_ctc1()
107 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_ctc1()
119 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_ctc1()
120 env->CP0_Config5 &= ~(1 << CP0C5_FRE); in helper_ctc1()
131 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_ctc1()
132 env->CP0_Config5 |= (1 << CP0C5_FRE); in helper_ctc1()
H A Dop_helper.c255 return (env->CP0_Config5 >> CP0C5_XNP) & 1; in helper_rdhwr_xnp()
H A Dtranslate.h29 int32_t CP0_Config5; member
/openbmc/qemu/target/mips/tcg/system/
H A Dcp0_helper.c1266 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1268 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1326 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/openbmc/qemu/target/mips/system/
H A Dmachine.c305 VMSTATE_INT32(env.CP0_Config5, MIPSCPU),