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Searched refs:CLK_TOP_SPI0_SEL (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt7629-clk.h92 #define CLK_TOP_SPI0_SEL 82 macro
H A Dmt7622-clk.h77 #define CLK_TOP_SPI0_SEL 65 macro
H A Dmt2701-clk.h97 #define CLK_TOP_SPI0_SEL 86 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h96 #define CLK_TOP_SPI0_SEL 82 macro
H A Dmt7623-clk.h110 #define CLK_TOP_SPI0_SEL 96 macro
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c521 MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
676 GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
687 GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
H A Dclk-mt7629.c139 FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
377 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c408 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
H A Dclk-mt7629.c482 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
H A Dclk-mt2701.c507 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi282 <&topckgen CLK_TOP_SPI0_SEL>,
H A Dmt2701.dtsi343 <&topckgen CLK_TOP_SPI0_SEL>,
H A Dmt7623.dtsi488 <&topckgen CLK_TOP_SPI0_SEL>,
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi499 <&topckgen CLK_TOP_SPI0_SEL>,