Searched refs:CLK_TOP_P0_1MHZ (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 23 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 267 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
|
| H A D | clk-mt7629.c | 366 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
|
| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 89 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
|