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Searched refs:CLK_TOP_MSDC30_3_SEL (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt8135-clk.h83 #define CLK_TOP_MSDC30_3_SEL 72 macro
H A Dmediatek,mt6795-clk.h107 #define CLK_TOP_MSDC30_3_SEL 96 macro
H A Dmt8173-clk.h109 #define CLK_TOP_MSDC30_3_SEL 99 macro
H A Dmt2712-clk.h146 #define CLK_TOP_MSDC30_3_SEL 115 macro
H A Dmt2701-clk.h126 #define CLK_TOP_MSDC30_3_SEL 115 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h139 #define CLK_TOP_MSDC30_3_SEL 125 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c477 TOP_MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x80, 8, 3, 15, 0),
H A Dclk-mt8173-topckgen.c559 MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
H A Dclk-mt8135.c368 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
H A Dclk-mt2712.c670 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
H A Dclk-mt2701.c573 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c559 MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
663 GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),