Searched refs:CLK_TOP_APLL_SEL (Results 1 – 8 of 8) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 102 #define CLK_TOP_APLL_SEL 91 macro
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| H A D | mt2712-clk.h | 170 #define CLK_TOP_APLL_SEL 139 macro
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| H A D | mt2701-clk.h | 107 #define CLK_TOP_APLL_SEL 96 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 123 #define CLK_TOP_APLL_SEL 109 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt8135.c | 395 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
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| H A D | clk-mt2712.c | 711 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x500, 8, 4, 15),
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| H A D | clk-mt2701.c | 536 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 537 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
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