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Searched refs:CLK_SET_RATE_GATE (Results 1 – 25 of 75) sorted by relevance

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/openbmc/linux/drivers/clk/ux500/
H A Du8500_of_clk.c233 CLK_SET_RATE_GATE); in u8500_clk_init()
238 CLK_SET_RATE_GATE); in u8500_clk_init()
241 CLK_SET_RATE_GATE); in u8500_clk_init()
244 CLK_SET_RATE_GATE); in u8500_clk_init()
249 CLK_SET_RATE_GATE); in u8500_clk_init()
262 CLK_SET_RATE_GATE); in u8500_clk_init()
276 CLK_SET_RATE_GATE); in u8500_clk_init()
279 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); in u8500_clk_init()
282 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); in u8500_clk_init()
285 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); in u8500_clk_init()
[all …]
/openbmc/linux/drivers/clk/baikal-t1/
H A Dclk-ccu-div.c137 CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
141 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
144 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
147 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
150 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
153 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
156 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
159 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
162 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
165 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
[all …]
H A Dclk-ccu-pll.c69 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
71 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
75 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0)
H A Dccu-div.c442 num += !!(div->flags & CLK_SET_RATE_GATE) + in ccu_div_var_debug_init()
451 if (!(div->flags & CLK_SET_RATE_GATE) && in ccu_div_var_debug_init()
604 if (hw_init.flags & CLK_SET_RATE_GATE) in ccu_div_hw_register()
/openbmc/linux/drivers/clk/at91/
H A Dsam9x60.c244 CLK_IS_CRITICAL | CLK_SET_RATE_GATE); in sam9x60_pmc_setup()
255 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); in sam9x60_pmc_setup()
264 &pll_frac_layout, CLK_SET_RATE_GATE); in sam9x60_pmc_setup()
271 CLK_SET_RATE_GATE | in sam9x60_pmc_setup()
291 CLK_SET_RATE_GATE, 0); in sam9x60_pmc_setup()
H A Dsama7g5.c213 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
226 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
242 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
252 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
263 .f = CLK_SET_RATE_GATE,
272 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
284 .f = CLK_SET_RATE_GATE, },
292 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
304 .f = CLK_SET_RATE_GATE,
313 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
[all …]
H A Dclk-audio-pll.c467 init.flags = CLK_SET_RATE_GATE; in at91_clk_register_audio_pll_frac()
497 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | in at91_clk_register_audio_pll_pad()
528 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | in at91_clk_register_audio_pll_pmc()
H A Dclk-plldiv.c90 init.flags = CLK_SET_RATE_GATE; in at91_clk_register_plldiv()
H A Dclk-h32mx.c100 init.flags = CLK_SET_RATE_GATE; in at91_clk_register_h32mx()
H A Dclk-smd.c129 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91sam9x5_clk_register_smd()
H A Dclk-usb.c240 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | in _at91sam9x5_clk_register_usb()
291 init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; in at91sam9n12_clk_register_usb()
H A Dat91sam9rl.c134 &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); in at91sam9rl_pmc_setup()
/openbmc/linux/drivers/clk/qcom/
H A Dlcc-ipq806x.c138 .flags = CLK_SET_RATE_GATE,
255 .flags = CLK_SET_RATE_GATE,
339 .flags = CLK_SET_RATE_GATE,
H A Dlcc-msm8960.c121 .flags = CLK_SET_RATE_GATE, \
283 .flags = CLK_SET_RATE_GATE,
353 .flags = CLK_SET_RATE_GATE,
H A Dgcc-mdm9615.c792 .flags = CLK_SET_RATE_GATE,
843 .flags = CLK_SET_RATE_GATE,
1066 .flags = CLK_SET_RATE_GATE,
1117 .flags = CLK_SET_RATE_GATE,
1173 .flags = CLK_SET_RATE_GATE,
1229 .flags = CLK_SET_RATE_GATE,
1285 .flags = CLK_SET_RATE_GATE,
H A Dgcc-ipq806x.c1217 .flags = CLK_SET_RATE_GATE,
1268 .flags = CLK_SET_RATE_GATE,
1688 .flags = CLK_SET_RATE_GATE,
1782 .flags = CLK_SET_RATE_GATE,
1876 .flags = CLK_SET_RATE_GATE,
1975 .flags = CLK_SET_RATE_GATE,
2116 .flags = CLK_SET_RATE_GATE,
2190 .flags = CLK_SET_RATE_GATE,
2264 .flags = CLK_SET_RATE_GATE,
2330 .flags = CLK_SET_RATE_GATE,
H A Dgcc-msm8960.c1677 .flags = CLK_SET_RATE_GATE,
1728 .flags = CLK_SET_RATE_GATE,
2101 .flags = CLK_SET_RATE_GATE,
2157 .flags = CLK_SET_RATE_GATE,
2208 .flags = CLK_SET_RATE_GATE,
2259 .flags = CLK_SET_RATE_GATE,
2310 .flags = CLK_SET_RATE_GATE,
2409 .flags = CLK_SET_RATE_GATE,
2478 .flags = CLK_SET_RATE_GATE,
2968 .flags = CLK_SET_RATE_GATE,
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-pfdv2.c227 init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; in imx_clk_hw_pfdv2()
229 init.flags = CLK_SET_RATE_GATE; in imx_clk_hw_pfdv2()
H A Dclk-imx7ulp.c77 … = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()
78 … = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()
102 …SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x60… in imx7ulp_clk_scg1_init()
H A Dclk-imx6sll.c176 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
178 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); in imx6sll_clocks_init()
180 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
182 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
H A Dclk-gpr-mux.c98 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in imx_clk_gpr_mux()
H A Dclk-imx6ul.c233 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
235 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); in imx6ul_clocks_init()
237 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
239 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
H A Dclk-imx7d.c430 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock); in imx7d_clocks_init()
432 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); in imx7d_clocks_init()
434 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
436 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock); in imx7d_clocks_init()
438 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
H A Dclk-composite-7ulp.c146 has_swrst ? &pcc_gate_ops : &clk_gate_ops, CLK_SET_RATE_GATE | in imx_ulp_clk_hw_composite()
/openbmc/linux/drivers/clk/
H A Dclk-fsl-sai.c65 CLK_SET_RATE_GATE); in fsl_sai_clk_probe()

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