Searched refs:CLK_INFRA_MUX1_SEL (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 121 #define CLK_INFRA_MUX1_SEL 0 macro
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| H A D | mt7622-clk.h | 125 #define CLK_INFRA_MUX1_SEL 0 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 125 #define CLK_INFRA_MUX1_SEL 0 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt7622-infracfg.c | 34 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2),
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| H A D | clk-mt7629.c | 456 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
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