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Searched refs:CLK_APMIXED_ETH1PLL (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c54 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
86 FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
87 FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
88 FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
89 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
90 FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
/openbmc/u-boot/arch/arm/mach-mediatek/mt7629/
H A Dinit.c32 [CLK_APMIXED_ETH1PLL] = 500000000, in mtk_pll_early_init()
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h162 #define CLK_APMIXED_ETH1PLL 3 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dmt7629-clk.h158 #define CLK_APMIXED_ETH1PLL 3 macro
H A Dmt7622-clk.h173 #define CLK_APMIXED_ETH1PLL 3 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7622-apmixedsys.c65 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
H A Dclk-mt7629.c319 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,