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Searched refs:CLKID_VCLK2_DIV1 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Daxg-clkc.h137 #define CLKID_VCLK2_DIV1 127 macro
H A Dgxbb-clkc.h198 #define CLKID_VCLK2_DIV1 190 macro
H A Dmeson8b-clkc.h158 #define CLKID_VCLK2_DIV1 151 macro
H A Dg12a-clkc.h164 #define CLKID_VCLK2_DIV1 153 macro
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.c2929 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3133 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3348 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
H A Dgxbb.c2919 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
3126 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
H A Dg12a.c4395 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4620 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4880 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
H A Daxg.c2022 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,