Searched refs:CCB (Results 1 – 14 of 14) sorted by relevance
/openbmc/u-boot/doc/ |
H A D | README.mpc85xxcds | 146 SW3=XX00XXXX == CORE:CCB 2:1 147 XX01XXXX == CORE:CCB 5:2 148 XX10XXXX == CORE:CCB 3:1 149 XX11XXXX == CORE:CCB 7:2 150 XXXX1000 == CCB:SYSCLK 8:1 151 XXXX1010 == CCB:SYSCLK 10:1 176 SW3=X000XXXX == CORE:CCB 4:1 177 X001XXXX == CORE:CCB 9:2 178 X010XXXX == CORE:CCB 1:1 179 X011XXXX == CORE:CCB 3:2 [all …]
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H A D | README.Heterogeneous-SoCs | 93 CCB:666.667 MHz,
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H A D | README.b4860qds | 130 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple 155 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
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/openbmc/linux/Documentation/arch/sparc/oradax/ |
H A D | dax-hv-api.txt | 138 Table 36.1. CCB Header Format 140 [31:28] CCB version. For API version 2.0: set to 1 if CCB uses OZIP encoding; set to 0 if the… 212 A CCB may only be conditional on exactly one CCB, however, a CCB may be marked both Conditional 217 the input of the next CCB (the "target" CCB). The target CCB thus does not need to read the input f… 221 target CCB. Exactly one CCB must be made conditional on the source CCB; either 0 or 2 target CCBs 416 The extract CCB is a 64-byte “short format” CCB. 438 0 4 CCB header (Table 36.1, “CCB Header Format”) 645 0 4 CCB header (Table 36.1, “CCB Header Format”) 847 The select CCB is a 64-byte “short format” CCB. 869 0 4 CCB header (Table 36.1, “CCB Header Format”) [all …]
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H A D | oracle-dax.rst | 34 (CCB). The CCB contains an opcode and various parameters. The opcode 40 there was an error. One of the addresses given in each CCB is a 124 Kills a CCB during execution. The CCB is guaranteed to not continue 187 - submit CCB via write() or pwrite() 232 CCB Structure 254 - CCB version, which must be consistent with hardware version 307 ccb->control = /* Table 36.1, CCB Header Format */ 311 /* Section 36.2.1, Query CCB Command Formats */ 334 The CCB submission is a write() or pwrite() system call to the 392 type must be given in the CCB:: [all …]
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/openbmc/u-boot/board/freescale/bsc9132qds/ |
H A D | README | 73 Core MHz/CCB MHz/DDR(MT/s) 74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz 76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
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/openbmc/linux/Documentation/scsi/ |
H A D | ChangeLog.ncr53c8xx | 358 Count actual number of CCB queued to the controller (future use). 379 - Add CCB done queue support for Alpha and perhaps some other 441 - New CCB starvation avoiding algorithm. 452 the scripts to jump directly to the CCB on reselection instead 459 Use a simple CALL to a launch script in the CCB. 464 - generalization of the restart of CCB on special condition as
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H A D | ChangeLog.sym53c8xx | 18 - In the CCB abort path, do not assume that the CCB is currently 25 handling. If the DSA didn't match a CCB, a bad write to 493 the done queue and returns if some completed CCB is found. If no 494 completed CCB are found, interrupt handling will proceed normally.
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H A D | ncr53c8xx.rst | 1460 that is moved by the SCRIPTS processor is the 'CCB header' that contains
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/openbmc/u-boot/board/freescale/bsc9131rdb/ |
H A D | README | 76 Core MHz/CCB MHz/DDR(MT/s)
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/openbmc/u-boot/board/freescale/p1010rdb/ |
H A D | README.P1010RDB-PA | 186 Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
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/openbmc/u-boot/board/sbc8548/ |
H A D | README | 37 to reflect a different CCB:SYSCLK ratio]
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/openbmc/linux/drivers/scsi/ |
H A D | FlashPoint.c | 7515 FlashPoint__StartCCB(void *CardHandle, struct blogic_ccb *CCB) in FlashPoint__StartCCB() argument 7517 FlashPoint_StartCCB(CardHandle, (struct sccb *)CCB); in FlashPoint__StartCCB() 7521 FlashPoint__AbortCCB(void *CardHandle, struct blogic_ccb *CCB) in FlashPoint__AbortCCB() argument 7523 FlashPoint_AbortCCB(CardHandle, (struct sccb *)CCB); in FlashPoint__AbortCCB()
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/openbmc/qemu/pc-bios/ |
H A D | qemu.rsrc | 560 $"5CCB F4F6 F6F5 F5F7 FCFE FEFE FEFE FEFE" /* \ÀÙˆˆıı˜¸˛˛˛˛˛˛˛ */
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