| /openbmc/u-boot/include/configs/ |
| H A D | usb_a9263.h | 42 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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| H A D | meesc.h | 58 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
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| H A D | at91sam9rlek.h | 44 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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| H A D | picosam9g45.h | 65 #define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */
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| H A D | at91sam9260ek.h | 56 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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| H A D | snapper9260.h | 30 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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| H A D | taurus.h | 61 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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| H A D | smartweb.h | 65 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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| H A D | at91sam9263ek.h | 55 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91sam9261.h | 106 #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ macro
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| H A D | at91sam9rl.h | 108 #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ macro
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| H A D | at91sam9263.h | 121 #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ macro
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| H A D | at91sam9g45.h | 126 #define ATMEL_BASE_CS1 0x20000000 macro
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| H A D | at91sam9260.h | 122 #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ macro
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| H A D | at91sam9x5.h | 128 #define ATMEL_BASE_CS1 0x20000000 macro
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| H A D | sama5d3.h | 177 #define ATMEL_BASE_CS1 0x40000000 macro
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| H A D | sama5d4.h | 163 #define ATMEL_BASE_CS1 0x60000000 macro
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| H A D | sama5d2.h | 134 #define ATMEL_BASE_CS1 0x60000000 macro
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| /openbmc/u-boot/board/laird/wb45n/ |
| H A D | wb45n.c | 196 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /openbmc/u-boot/board/atmel/at91sam9x5ek/ |
| H A D | at91sam9x5ek.c | 206 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /openbmc/u-boot/board/siemens/smartweb/ |
| H A D | smartweb.c | 256 sdramc_initialize(ATMEL_BASE_CS1, &setting); in mem_init()
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| /openbmc/u-boot/board/atmel/at91sam9n12ek/ |
| H A D | at91sam9n12ek.c | 289 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /openbmc/u-boot/board/mini-box/picosam9g45/ |
| H A D | picosam9g45.c | 98 ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /openbmc/u-boot/board/siemens/taurus/ |
| H A D | taurus.c | 175 sdramc_initialize(ATMEL_BASE_CS1, &setting); in sdramc_configure()
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| /openbmc/u-boot/board/bluewater/gurnard/ |
| H A D | gurnard.c | 215 writel(0, ATMEL_BASE_CS1); in fpga_hw_init()
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