Searched refs:AIPS1_OFF_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance
172 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) macro173 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)174 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)175 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)176 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)177 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)178 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)180 #define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)181 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)182 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)[all …]
86 #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) macro88 #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR95 #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)96 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)97 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)98 #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)99 #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)100 #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)101 #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)103 #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)[all …]