/openbmc/linux/Documentation/devicetree/bindings/display/panel/ |
H A D | display-timings.yaml | 18 and to specify the timing that is native for the display. 27 The default display timing is the one specified as native-mode. 32 "^timing": 34 $ref: panel-timing.yaml# 42 * Example that specifies panel timing using minimum, typical,
|
H A D | panel-timing.yaml | 4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml# 7 title: panel timing 14 There are different ways of describing the timing data of a panel. The 46 This matches the timing diagrams often found in data sheets. 73 description: Horizontal front porch panel timing 85 description: Horizontal back porch timing 97 description: Horizontal sync length panel timing 109 description: Vertical front porch panel timing 121 description: Vertical back porch panel timing 133 description: Vertical sync length panel timing
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce80/ |
H A D | dce80_timing_generator.c | 109 const struct dc_crtc_timing *timing, in program_timing() argument 118 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing() 120 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing() 126 const struct dc_crtc_timing *timing) in dce80_timing_generator_enable_advanced_request() argument 146 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce80_timing_generator_enable_advanced_request()
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
H A D | link_hwss_hpo_dp.c | 50 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in set_hpo_dp_hblank_min_symbol_width() local 59 timing->h_total - timing->h_addressable), in set_hpo_dp_hblank_min_symbol_width() 60 dc_fixpt_from_fraction(timing->pix_clk_100hz, 10)); in set_hpo_dp_hblank_min_symbol_width() 96 &stream->timing, in setup_hpo_dp_stream_attribute() 99 stream->timing.flags.DSC, in setup_hpo_dp_stream_attribute()
|
/openbmc/u-boot/drivers/video/ |
H A D | ihs_video_out.c | 237 struct display_timing timing; in ihs_video_out_probe() local 260 timing.hactive.typ = 1024; in ihs_video_out_probe() 261 timing.vactive.typ = 768; in ihs_video_out_probe() 266 timing.hactive.typ = 720; in ihs_video_out_probe() 267 timing.vactive.typ = 400; in ihs_video_out_probe() 272 timing.hactive.typ = 640; in ihs_video_out_probe() 273 timing.vactive.typ = 480; in ihs_video_out_probe() 324 res = display_enable(priv->video_tx, 8, &timing); in ihs_video_out_probe()
|
/openbmc/linux/drivers/mmc/host/ |
H A D | sdhci-xenon.c | 197 unsigned int timing) in xenon_set_uhs_signaling() argument 204 if (timing == MMC_TIMING_MMC_HS200) in xenon_set_uhs_signaling() 206 else if (timing == MMC_TIMING_UHS_SDR104) in xenon_set_uhs_signaling() 208 else if (timing == MMC_TIMING_UHS_SDR12) in xenon_set_uhs_signaling() 210 else if (timing == MMC_TIMING_UHS_SDR25) in xenon_set_uhs_signaling() 212 else if (timing == MMC_TIMING_UHS_SDR50) in xenon_set_uhs_signaling() 214 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling() 215 (timing == MMC_TIMING_MMC_DDR52)) in xenon_set_uhs_signaling() 217 else if (timing == MMC_TIMING_MMC_HS400) in xenon_set_uhs_signaling() 292 (ios->timing == MMC_TIMING_MMC_HS)) { in xenon_set_ios() [all …]
|
H A D | sdhci-xenon-phy.c | 520 unsigned char timing) in xenon_emmc_phy_slow_mode() argument 536 switch (timing) { in xenon_emmc_phy_slow_mode() 575 unsigned char timing) in xenon_emmc_phy_set() argument 606 if (timing == MMC_TIMING_LEGACY) { in xenon_emmc_phy_set() 644 switch (timing) { in xenon_emmc_phy_set() 667 if (timing == MMC_TIMING_MMC_HS400) in xenon_emmc_phy_set() 776 switch (host->timing) { in xenon_hs_delay_adj() 828 (ios->timing == priv->timing)) in xenon_phy_adj() 831 xenon_emmc_phy_set(host, ios->timing); in xenon_phy_adj() 836 priv->timing = ios->timing; in xenon_phy_adj() [all …]
|
H A D | dw_mmc-k3.c | 216 static void dw_mci_hs_set_timing(struct dw_mci *host, int timing, in dw_mci_hs_set_timing() argument 230 drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase; in dw_mci_hs_set_timing() 231 smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly; in dw_mci_hs_set_timing() 233 smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max + in dw_mci_hs_set_timing() 234 hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2; in dw_mci_hs_set_timing() 236 switch (timing) { in dw_mci_hs_set_timing() 315 dw_mci_hs_set_timing(host, ios->timing, -1); in dw_mci_hi3660_set_ios() 380 dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase); in dw_mci_hi3660_execute_tuning() 394 dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl); in dw_mci_hi3660_execute_tuning()
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
H A D | dce60_timing_generator.c | 109 const struct dc_crtc_timing *timing, in program_timing() argument 118 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing() 120 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing() 126 const struct dc_crtc_timing *timing) in dce60_timing_generator_enable_advanced_request() argument 138 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce60_timing_generator_enable_advanced_request()
|
/openbmc/linux/drivers/memory/tegra/ |
H A D | tegra20-emc.c | 264 timing = &emc->timings[i]; in tegra_emc_find_timing() 269 if (!timing) { in tegra_emc_find_timing() 274 return timing; in tegra_emc_find_timing() 282 if (!timing) in emc_prepare_timing_change() 286 __func__, timing->rate, rate); in emc_prepare_timing_change() 375 timing->data, in load_one_timing_from_dt() 414 struct emc_timing *timing; in tegra_emc_load_timings_from_dt() local 429 timing = emc->timings; in tegra_emc_load_timings_from_dt() 703 timing = &emc->timings[i]; in emc_round_rate() 707 if (!timing) { in emc_round_rate() [all …]
|
H A D | tegra210-emc-core.c | 1228 timing = emc->last; in tegra210_emc_dvfs_power_ramp_up() 1230 timing = emc->next; in tegra210_emc_dvfs_power_ramp_up() 1445 timing->current_dram_clktree[C0D0U0] = in tegra210_emc_reset_dram_clktree_values() 1446 timing->trained_dram_clktree[C0D0U0]; in tegra210_emc_reset_dram_clktree_values() 1447 timing->current_dram_clktree[C0D0U1] = in tegra210_emc_reset_dram_clktree_values() 1448 timing->trained_dram_clktree[C0D0U1]; in tegra210_emc_reset_dram_clktree_values() 1543 timing = &emc->timings[i]; in tegra210_emc_set_rate() 1548 if (!timing) in tegra210_emc_set_rate() 1554 emc->next = timing; in tegra210_emc_set_rate() 1565 emc->last = timing; in tegra210_emc_set_rate() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | cdns,sdhci.yaml | 40 description: Value of the delay in the input path for SD high-speed timing 46 description: Value of the delay in the input path for legacy timing 52 description: Value of the delay in the input path for SD UHS SDR12 timing 58 description: Value of the delay in the input path for SD UHS SDR25 timing 64 description: Value of the delay in the input path for SD UHS SDR50 timing 70 description: Value of the delay in the input path for SD UHS DDR50 timing 76 description: Value of the delay in the input path for MMC high-speed timing 82 description: Value of the delay in the input path for eMMC high-speed DDR timing
|
/openbmc/u-boot/drivers/video/sunxi/ |
H A D | sunxi_display.c | 616 struct display_timing *timing) in sunxi_ctfb_mode_to_display_timing() argument 620 timing->hactive.typ = mode->xres; in sunxi_ctfb_mode_to_display_timing() 623 timing->hsync_len.typ = mode->hsync_len; in sunxi_ctfb_mode_to_display_timing() 625 timing->vactive.typ = mode->yres; in sunxi_ctfb_mode_to_display_timing() 628 timing->vsync_len.typ = mode->vsync_len; in sunxi_ctfb_mode_to_display_timing() 630 timing->flags = 0; in sunxi_ctfb_mode_to_display_timing() 633 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; in sunxi_ctfb_mode_to_display_timing() 635 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; in sunxi_ctfb_mode_to_display_timing() 639 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; in sunxi_ctfb_mode_to_display_timing() 652 struct display_timing timing; local [all …]
|
/openbmc/linux/drivers/gpu/drm/sti/ |
H A D | sti_dvo.c | 58 struct awg_timing *timing); 117 struct awg_timing timing; in dvo_awg_generate_code() local 122 timing.total_lines = mode->vtotal; in dvo_awg_generate_code() 123 timing.active_lines = mode->vdisplay; in dvo_awg_generate_code() 124 timing.blanking_lines = mode->vsync_start - mode->vdisplay; in dvo_awg_generate_code() 125 timing.trailing_lines = mode->vtotal - mode->vsync_start; in dvo_awg_generate_code() 126 timing.total_pixels = mode->htotal; in dvo_awg_generate_code() 127 timing.active_pixels = mode->hdisplay; in dvo_awg_generate_code() 129 timing.trailing_pixels = mode->htotal - mode->hsync_start; in dvo_awg_generate_code() 130 timing.blanking_level = BLANKING_LEVEL; in dvo_awg_generate_code() [all …]
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_resource.c | 532 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ in resource_are_vblanks_synchronizable() 535 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ in resource_are_vblanks_synchronizable() 561 if (stream1->timing.h_total != stream2->timing.h_total) in resource_are_streams_timing_synchronizable() 564 if (stream1->timing.v_total != stream2->timing.v_total) in resource_are_streams_timing_synchronizable() 1391 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in resource_build_scaling_params() local 2120 &cur_stream->timing, in dc_is_timing_changed() 2121 &new_stream->timing, in dc_is_timing_changed() 2581 &stream->timing) / 10; in calculate_phy_pix_clks() 3568 &stream->timing, in set_adaptive_sync_info_packet() 3948 &stream->timing); in dc_validate_stream() [all …]
|
/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra124-nyan-blaze-emc.dtsi | 10 timing-12750000 { 17 timing-20400000 { 24 timing-40800000 { 31 timing-68000000 { 38 timing-102000000 { 45 timing-204000000 { 52 timing-300000000 { 59 timing-396000000 { 68 timing-600000000 { 88 timing-12750000 { [all …]
|
H A D | tegra30-asus-tf300tg.dts | 224 timing-25500000 { 234 timing-51000000 { 244 timing-102000000 { 254 timing-204000000 { 264 timing-333500000 { 289 timing-25500000 { 299 timing-51000000 { 354 timing-25500000 { 364 timing-51000000 { 421 timing-25500000 { [all …]
|
H A D | tegra30-asus-tf300t.dts | 150 timing-25500000 { 160 timing-51000000 { 170 timing-102000000 { 180 timing-204000000 { 190 timing-333500000 { 200 timing-667000000 { 215 timing-25500000 { 225 timing-51000000 { 280 timing-25500000 { 290 timing-51000000 { [all …]
|
H A D | tegra124-jetson-tk1-emc.dtsi | 10 timing-12750000 { 17 timing-20400000 { 24 timing-40800000 { 31 timing-68000000 { 38 timing-102000000 { 45 timing-204000000 { 52 timing-300000000 { 59 timing-396000000 { 66 timing-528000000 { 100 timing-12750000 { [all …]
|
H A D | tegra124-apalis-emc.dtsi | 14 timing-12750000 { 21 timing-20400000 { 28 timing-40800000 { 35 timing-68000000 { 42 timing-102000000 { 49 timing-204000000 { 56 timing-300000000 { 63 timing-396000000 { 70 timing-528000000 { 104 timing-12750000 { [all …]
|
/openbmc/qemu/hw/display/ |
H A D | pl110.c | 63 uint32_t timing[4]; member 88 VMSTATE_UINT32_ARRAY(timing, PL110State, 4), 403 return s->timing[0]; in pl110_read() 405 return s->timing[1]; in pl110_read() 407 return s->timing[2]; in pl110_read() 409 return s->timing[3]; in pl110_read() 458 s->timing[0] = val; in pl110_write() 463 s->timing[1] = val; in pl110_write() 468 s->timing[2] = val; in pl110_write() 471 s->timing[3] = val; in pl110_write()
|
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/ |
H A D | st,stm32-fmc.txt | 18 - st,sdram-timing: timings for sdram, in this order: 27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing 47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
H A D | dce110_timing_generator.h | 129 const struct dc_crtc_timing *timing, 203 const struct dc_crtc_timing *timing); 247 const struct dc_crtc_timing *timing); 259 const struct dc_crtc_timing *timing, 273 const struct dc_crtc_timing *timing);
|
/openbmc/u-boot/doc/device-tree-bindings/video/ |
H A D | display-timing.txt | 1 display-timing bindings 14 timing subnode 19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters 21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in 99 timing1: timing {
|
/openbmc/openbmc/poky/meta/recipes-devtools/python/python3/ |
H A D | 0001-Skip-failing-tests-due-to-load-variability-on-YP-AB.patch | 33 + @unittest.skip('timing related test, dependent on load') 41 + @unittest.skip('timing related test, dependent on load') 49 + @unittest.skip('timing related test, dependent on load') 61 + @unittest.skip('timing related test, dependent on load') 69 + @unittest.skip('timing related test, dependent on load')
|