12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2036f29d5SZhangfei Gao /*
3036f29d5SZhangfei Gao * Copyright (c) 2013 Linaro Ltd.
447805532SHao Fang * Copyright (c) 2013 HiSilicon Limited.
5036f29d5SZhangfei Gao */
6036f29d5SZhangfei Gao
7361c7fe9Sliwei #include <linux/bitops.h>
8361c7fe9Sliwei #include <linux/bitfield.h>
9036f29d5SZhangfei Gao #include <linux/clk.h>
100293efddSZhangfei Gao #include <linux/mfd/syscon.h>
11036f29d5SZhangfei Gao #include <linux/mmc/host.h>
120293efddSZhangfei Gao #include <linux/module.h>
13036f29d5SZhangfei Gao #include <linux/of_address.h>
140293efddSZhangfei Gao #include <linux/platform_device.h>
152c8ae20eSShawn Lin #include <linux/pm_runtime.h>
160293efddSZhangfei Gao #include <linux/regmap.h>
170293efddSZhangfei Gao #include <linux/regulator/consumer.h>
18036f29d5SZhangfei Gao
19036f29d5SZhangfei Gao #include "dw_mmc.h"
20036f29d5SZhangfei Gao #include "dw_mmc-pltfm.h"
21036f29d5SZhangfei Gao
220293efddSZhangfei Gao /*
230293efddSZhangfei Gao * hi6220 sd only support io voltage 1.8v and 3v
240293efddSZhangfei Gao * Also need config AO_SCTRL_SEL18 accordingly
250293efddSZhangfei Gao */
260293efddSZhangfei Gao #define AO_SCTRL_SEL18 BIT(10)
270293efddSZhangfei Gao #define AO_SCTRL_CTRL3 0x40C
280293efddSZhangfei Gao
29361c7fe9Sliwei #define DWMMC_SDIO_ID 2
30361c7fe9Sliwei
31361c7fe9Sliwei #define SOC_SCTRL_SCPERCTRL5 (0x314)
32361c7fe9Sliwei #define SDCARD_IO_SEL18 BIT(2)
33361c7fe9Sliwei
34361c7fe9Sliwei #define SDCARD_RD_THRESHOLD (512)
35361c7fe9Sliwei
36361c7fe9Sliwei #define GENCLK_DIV (7)
37361c7fe9Sliwei
38361c7fe9Sliwei #define GPIO_CLK_ENABLE BIT(16)
39361c7fe9Sliwei #define GPIO_CLK_DIV_MASK GENMASK(11, 8)
40361c7fe9Sliwei #define GPIO_USE_SAMPLE_DLY_MASK GENMASK(13, 13)
41361c7fe9Sliwei #define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
42361c7fe9Sliwei #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK GENMASK(25, 21)
43361c7fe9Sliwei #define UHS_REG_EXT_SAMPLE_DLY_MASK GENMASK(30, 26)
44361c7fe9Sliwei
45361c7fe9Sliwei #define TIMING_MODE 3
46361c7fe9Sliwei #define TIMING_CFG_NUM 10
47361c7fe9Sliwei
48361c7fe9Sliwei #define NUM_PHASES (40)
49361c7fe9Sliwei
50361c7fe9Sliwei #define ENABLE_SHIFT_MIN_SMPL (4)
51361c7fe9Sliwei #define ENABLE_SHIFT_MAX_SMPL (12)
52361c7fe9Sliwei #define USE_DLY_MIN_SMPL (11)
53361c7fe9Sliwei #define USE_DLY_MAX_SMPL (14)
54361c7fe9Sliwei
550293efddSZhangfei Gao struct k3_priv {
56361c7fe9Sliwei int ctrl_id;
57361c7fe9Sliwei u32 cur_speed;
580293efddSZhangfei Gao struct regmap *reg;
590293efddSZhangfei Gao };
600293efddSZhangfei Gao
61af637629SJérôme Forissier static unsigned long dw_mci_hi6220_caps[] = {
62af637629SJérôme Forissier MMC_CAP_CMD23,
63af637629SJérôme Forissier MMC_CAP_CMD23,
64af637629SJérôme Forissier 0
65af637629SJérôme Forissier };
66af637629SJérôme Forissier
67361c7fe9Sliwei struct hs_timing {
68361c7fe9Sliwei u32 drv_phase;
69361c7fe9Sliwei u32 smpl_dly;
70361c7fe9Sliwei u32 smpl_phase_max;
71361c7fe9Sliwei u32 smpl_phase_min;
72361c7fe9Sliwei };
73361c7fe9Sliwei
74085cc3abSColin Ian King static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
75361c7fe9Sliwei { /* reserved */ },
76361c7fe9Sliwei { /* SD */
77361c7fe9Sliwei {7, 0, 15, 15,}, /* 0: LEGACY 400k */
78361c7fe9Sliwei {6, 0, 4, 4,}, /* 1: MMC_HS */
79361c7fe9Sliwei {6, 0, 3, 3,}, /* 2: SD_HS */
80361c7fe9Sliwei {6, 0, 15, 15,}, /* 3: SDR12 */
81361c7fe9Sliwei {6, 0, 2, 2,}, /* 4: SDR25 */
82361c7fe9Sliwei {4, 0, 11, 0,}, /* 5: SDR50 */
83361c7fe9Sliwei {6, 4, 15, 0,}, /* 6: SDR104 */
84361c7fe9Sliwei {0}, /* 7: DDR50 */
85361c7fe9Sliwei {0}, /* 8: DDR52 */
86361c7fe9Sliwei {0}, /* 9: HS200 */
87361c7fe9Sliwei },
88361c7fe9Sliwei { /* SDIO */
89361c7fe9Sliwei {7, 0, 15, 15,}, /* 0: LEGACY 400k */
90361c7fe9Sliwei {0}, /* 1: MMC_HS */
91361c7fe9Sliwei {6, 0, 15, 15,}, /* 2: SD_HS */
92361c7fe9Sliwei {6, 0, 15, 15,}, /* 3: SDR12 */
93361c7fe9Sliwei {6, 0, 0, 0,}, /* 4: SDR25 */
94361c7fe9Sliwei {4, 0, 12, 0,}, /* 5: SDR50 */
95361c7fe9Sliwei {5, 4, 15, 0,}, /* 6: SDR104 */
96361c7fe9Sliwei {0}, /* 7: DDR50 */
97361c7fe9Sliwei {0}, /* 8: DDR52 */
98361c7fe9Sliwei {0}, /* 9: HS200 */
99361c7fe9Sliwei }
100361c7fe9Sliwei };
101361c7fe9Sliwei
dw_mci_k3_set_ios(struct dw_mci * host,struct mmc_ios * ios)102036f29d5SZhangfei Gao static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
103036f29d5SZhangfei Gao {
104036f29d5SZhangfei Gao int ret;
105036f29d5SZhangfei Gao
1060e662440SZhangfei Gao ret = clk_set_rate(host->ciu_clk, ios->clock);
107036f29d5SZhangfei Gao if (ret)
1080e662440SZhangfei Gao dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
109036f29d5SZhangfei Gao
110036f29d5SZhangfei Gao host->bus_hz = clk_get_rate(host->ciu_clk);
111036f29d5SZhangfei Gao }
112036f29d5SZhangfei Gao
113036f29d5SZhangfei Gao static const struct dw_mci_drv_data k3_drv_data = {
114036f29d5SZhangfei Gao .set_ios = dw_mci_k3_set_ios,
115036f29d5SZhangfei Gao };
116036f29d5SZhangfei Gao
dw_mci_hi6220_parse_dt(struct dw_mci * host)1170293efddSZhangfei Gao static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
1180293efddSZhangfei Gao {
1190293efddSZhangfei Gao struct k3_priv *priv;
1200293efddSZhangfei Gao
1210293efddSZhangfei Gao priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
1220293efddSZhangfei Gao if (!priv)
1230293efddSZhangfei Gao return -ENOMEM;
1240293efddSZhangfei Gao
1250293efddSZhangfei Gao priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node,
1260293efddSZhangfei Gao "hisilicon,peripheral-syscon");
1270293efddSZhangfei Gao if (IS_ERR(priv->reg))
1280293efddSZhangfei Gao priv->reg = NULL;
1290293efddSZhangfei Gao
130361c7fe9Sliwei priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
131361c7fe9Sliwei if (priv->ctrl_id < 0)
132361c7fe9Sliwei priv->ctrl_id = 0;
133361c7fe9Sliwei
134325501d9SGeert Uytterhoeven if (priv->ctrl_id >= TIMING_MODE)
135325501d9SGeert Uytterhoeven return -EINVAL;
136325501d9SGeert Uytterhoeven
1370293efddSZhangfei Gao host->priv = priv;
1380293efddSZhangfei Gao return 0;
1390293efddSZhangfei Gao }
1400293efddSZhangfei Gao
dw_mci_hi6220_switch_voltage(struct mmc_host * mmc,struct mmc_ios * ios)1410293efddSZhangfei Gao static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1420293efddSZhangfei Gao {
1430293efddSZhangfei Gao struct dw_mci_slot *slot = mmc_priv(mmc);
1440293efddSZhangfei Gao struct k3_priv *priv;
1450293efddSZhangfei Gao struct dw_mci *host;
1460293efddSZhangfei Gao int min_uv, max_uv;
1470293efddSZhangfei Gao int ret;
1480293efddSZhangfei Gao
1490293efddSZhangfei Gao host = slot->host;
1500293efddSZhangfei Gao priv = host->priv;
1510293efddSZhangfei Gao
1520293efddSZhangfei Gao if (!priv || !priv->reg)
1530293efddSZhangfei Gao return 0;
1540293efddSZhangfei Gao
1550293efddSZhangfei Gao if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1560293efddSZhangfei Gao ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
1570293efddSZhangfei Gao AO_SCTRL_SEL18, 0);
1580293efddSZhangfei Gao min_uv = 3000000;
1590293efddSZhangfei Gao max_uv = 3000000;
1600293efddSZhangfei Gao } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1610293efddSZhangfei Gao ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
1620293efddSZhangfei Gao AO_SCTRL_SEL18, AO_SCTRL_SEL18);
1630293efddSZhangfei Gao min_uv = 1800000;
1640293efddSZhangfei Gao max_uv = 1800000;
1650293efddSZhangfei Gao } else {
1660293efddSZhangfei Gao dev_dbg(host->dev, "voltage not supported\n");
1670293efddSZhangfei Gao return -EINVAL;
1680293efddSZhangfei Gao }
1690293efddSZhangfei Gao
1700293efddSZhangfei Gao if (ret) {
1710293efddSZhangfei Gao dev_dbg(host->dev, "switch voltage failed\n");
1720293efddSZhangfei Gao return ret;
1730293efddSZhangfei Gao }
1740293efddSZhangfei Gao
1750293efddSZhangfei Gao if (IS_ERR_OR_NULL(mmc->supply.vqmmc))
1760293efddSZhangfei Gao return 0;
1770293efddSZhangfei Gao
1780293efddSZhangfei Gao ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1790293efddSZhangfei Gao if (ret) {
1800293efddSZhangfei Gao dev_dbg(host->dev, "Regulator set error %d: %d - %d\n",
1810293efddSZhangfei Gao ret, min_uv, max_uv);
1820293efddSZhangfei Gao return ret;
1830293efddSZhangfei Gao }
1840293efddSZhangfei Gao
1850293efddSZhangfei Gao return 0;
1860293efddSZhangfei Gao }
1870293efddSZhangfei Gao
dw_mci_hi6220_set_ios(struct dw_mci * host,struct mmc_ios * ios)1880293efddSZhangfei Gao static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
1890293efddSZhangfei Gao {
1900293efddSZhangfei Gao int ret;
1910293efddSZhangfei Gao unsigned int clock;
1920293efddSZhangfei Gao
1930293efddSZhangfei Gao clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
1940293efddSZhangfei Gao
1950293efddSZhangfei Gao ret = clk_set_rate(host->biu_clk, clock);
1960293efddSZhangfei Gao if (ret)
1970293efddSZhangfei Gao dev_warn(host->dev, "failed to set rate %uHz\n", clock);
1980293efddSZhangfei Gao
1990293efddSZhangfei Gao host->bus_hz = clk_get_rate(host->biu_clk);
2000293efddSZhangfei Gao }
2010293efddSZhangfei Gao
dw_mci_hi6220_execute_tuning(struct dw_mci_slot * slot,u32 opcode)2023203a827SJin Guojun static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
2033203a827SJin Guojun {
2043203a827SJin Guojun return 0;
2053203a827SJin Guojun }
2063203a827SJin Guojun
2070293efddSZhangfei Gao static const struct dw_mci_drv_data hi6220_data = {
208af637629SJérôme Forissier .caps = dw_mci_hi6220_caps,
2090d84b9e5SShawn Lin .num_caps = ARRAY_SIZE(dw_mci_hi6220_caps),
2100293efddSZhangfei Gao .switch_voltage = dw_mci_hi6220_switch_voltage,
2110293efddSZhangfei Gao .set_ios = dw_mci_hi6220_set_ios,
2120293efddSZhangfei Gao .parse_dt = dw_mci_hi6220_parse_dt,
2133203a827SJin Guojun .execute_tuning = dw_mci_hi6220_execute_tuning,
2140293efddSZhangfei Gao };
2150293efddSZhangfei Gao
dw_mci_hs_set_timing(struct dw_mci * host,int timing,int smpl_phase)216361c7fe9Sliwei static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
217361c7fe9Sliwei int smpl_phase)
218361c7fe9Sliwei {
219361c7fe9Sliwei u32 drv_phase;
220361c7fe9Sliwei u32 smpl_dly;
221361c7fe9Sliwei u32 use_smpl_dly = 0;
222361c7fe9Sliwei u32 enable_shift = 0;
223361c7fe9Sliwei u32 reg_value;
224361c7fe9Sliwei int ctrl_id;
225361c7fe9Sliwei struct k3_priv *priv;
226361c7fe9Sliwei
227361c7fe9Sliwei priv = host->priv;
228361c7fe9Sliwei ctrl_id = priv->ctrl_id;
229361c7fe9Sliwei
230361c7fe9Sliwei drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
231361c7fe9Sliwei smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly;
232361c7fe9Sliwei if (smpl_phase == -1)
233361c7fe9Sliwei smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
234361c7fe9Sliwei hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
235361c7fe9Sliwei
236361c7fe9Sliwei switch (timing) {
237361c7fe9Sliwei case MMC_TIMING_UHS_SDR104:
238361c7fe9Sliwei if (smpl_phase >= USE_DLY_MIN_SMPL &&
239361c7fe9Sliwei smpl_phase <= USE_DLY_MAX_SMPL)
240361c7fe9Sliwei use_smpl_dly = 1;
241df561f66SGustavo A. R. Silva fallthrough;
242361c7fe9Sliwei case MMC_TIMING_UHS_SDR50:
243361c7fe9Sliwei if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
244361c7fe9Sliwei smpl_phase <= ENABLE_SHIFT_MAX_SMPL)
245361c7fe9Sliwei enable_shift = 1;
246361c7fe9Sliwei break;
247361c7fe9Sliwei }
248361c7fe9Sliwei
249361c7fe9Sliwei mci_writel(host, GPIO, 0x0);
250361c7fe9Sliwei usleep_range(5, 10);
251361c7fe9Sliwei
252361c7fe9Sliwei reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
253361c7fe9Sliwei FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) |
254361c7fe9Sliwei FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase);
255361c7fe9Sliwei mci_writel(host, UHS_REG_EXT, reg_value);
256361c7fe9Sliwei
257361c7fe9Sliwei mci_writel(host, ENABLE_SHIFT, enable_shift);
258361c7fe9Sliwei
259361c7fe9Sliwei reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) |
260361c7fe9Sliwei FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly);
261361c7fe9Sliwei mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);
262361c7fe9Sliwei
263361c7fe9Sliwei /* We should delay 1ms wait for timing setting finished. */
264361c7fe9Sliwei usleep_range(1000, 2000);
265361c7fe9Sliwei }
266361c7fe9Sliwei
dw_mci_hi3660_init(struct dw_mci * host)267361c7fe9Sliwei static int dw_mci_hi3660_init(struct dw_mci *host)
268361c7fe9Sliwei {
269361c7fe9Sliwei mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD,
270361c7fe9Sliwei SDMMC_CARD_RD_THR_EN));
271361c7fe9Sliwei
272361c7fe9Sliwei dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1);
273361c7fe9Sliwei host->bus_hz /= (GENCLK_DIV + 1);
274361c7fe9Sliwei
275361c7fe9Sliwei return 0;
276361c7fe9Sliwei }
277361c7fe9Sliwei
dw_mci_set_sel18(struct dw_mci * host,bool set)278361c7fe9Sliwei static int dw_mci_set_sel18(struct dw_mci *host, bool set)
279361c7fe9Sliwei {
280361c7fe9Sliwei int ret;
281361c7fe9Sliwei unsigned int val;
282361c7fe9Sliwei struct k3_priv *priv;
283361c7fe9Sliwei
284361c7fe9Sliwei priv = host->priv;
285361c7fe9Sliwei
286361c7fe9Sliwei val = set ? SDCARD_IO_SEL18 : 0;
287361c7fe9Sliwei ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5,
288361c7fe9Sliwei SDCARD_IO_SEL18, val);
289361c7fe9Sliwei if (ret) {
290361c7fe9Sliwei dev_err(host->dev, "sel18 %u error\n", val);
291361c7fe9Sliwei return ret;
292361c7fe9Sliwei }
293361c7fe9Sliwei
294361c7fe9Sliwei return 0;
295361c7fe9Sliwei }
296361c7fe9Sliwei
dw_mci_hi3660_set_ios(struct dw_mci * host,struct mmc_ios * ios)297361c7fe9Sliwei static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios)
298361c7fe9Sliwei {
299361c7fe9Sliwei int ret;
300361c7fe9Sliwei unsigned long wanted;
301361c7fe9Sliwei unsigned long actual;
302361c7fe9Sliwei struct k3_priv *priv = host->priv;
303361c7fe9Sliwei
304361c7fe9Sliwei if (!ios->clock || ios->clock == priv->cur_speed)
305361c7fe9Sliwei return;
306361c7fe9Sliwei
307361c7fe9Sliwei wanted = ios->clock * (GENCLK_DIV + 1);
308361c7fe9Sliwei ret = clk_set_rate(host->ciu_clk, wanted);
309361c7fe9Sliwei if (ret) {
310361c7fe9Sliwei dev_err(host->dev, "failed to set rate %luHz\n", wanted);
311361c7fe9Sliwei return;
312361c7fe9Sliwei }
313361c7fe9Sliwei actual = clk_get_rate(host->ciu_clk);
314361c7fe9Sliwei
315361c7fe9Sliwei dw_mci_hs_set_timing(host, ios->timing, -1);
316361c7fe9Sliwei host->bus_hz = actual / (GENCLK_DIV + 1);
317361c7fe9Sliwei host->current_speed = 0;
318361c7fe9Sliwei priv->cur_speed = host->bus_hz;
319361c7fe9Sliwei }
320361c7fe9Sliwei
dw_mci_get_best_clksmpl(unsigned int sample_flag)321361c7fe9Sliwei static int dw_mci_get_best_clksmpl(unsigned int sample_flag)
322361c7fe9Sliwei {
323361c7fe9Sliwei int i;
324361c7fe9Sliwei int interval;
325361c7fe9Sliwei unsigned int v;
326361c7fe9Sliwei unsigned int len;
327361c7fe9Sliwei unsigned int range_start = 0;
328361c7fe9Sliwei unsigned int range_length = 0;
329361c7fe9Sliwei unsigned int middle_range = 0;
330361c7fe9Sliwei
331361c7fe9Sliwei if (!sample_flag)
332361c7fe9Sliwei return -EIO;
333361c7fe9Sliwei
334361c7fe9Sliwei if (~sample_flag == 0)
335361c7fe9Sliwei return 0;
336361c7fe9Sliwei
337361c7fe9Sliwei i = ffs(sample_flag) - 1;
338361c7fe9Sliwei
339361c7fe9Sliwei /*
340361c7fe9Sliwei * A clock cycle is divided into 32 phases,
341361c7fe9Sliwei * each of which is represented by a bit,
342361c7fe9Sliwei * finding the optimal phase.
343361c7fe9Sliwei */
344361c7fe9Sliwei while (i < 32) {
345361c7fe9Sliwei v = ror32(sample_flag, i);
346361c7fe9Sliwei len = ffs(~v) - 1;
347361c7fe9Sliwei
348361c7fe9Sliwei if (len > range_length) {
349361c7fe9Sliwei range_length = len;
350361c7fe9Sliwei range_start = i;
351361c7fe9Sliwei }
352361c7fe9Sliwei
353361c7fe9Sliwei interval = ffs(v >> len) - 1;
354361c7fe9Sliwei if (interval < 0)
355361c7fe9Sliwei break;
356361c7fe9Sliwei
357361c7fe9Sliwei i += len + interval;
358361c7fe9Sliwei }
359361c7fe9Sliwei
360361c7fe9Sliwei middle_range = range_start + range_length / 2;
361361c7fe9Sliwei if (middle_range >= 32)
362361c7fe9Sliwei middle_range %= 32;
363361c7fe9Sliwei
364361c7fe9Sliwei return middle_range;
365361c7fe9Sliwei }
366361c7fe9Sliwei
dw_mci_hi3660_execute_tuning(struct dw_mci_slot * slot,u32 opcode)367361c7fe9Sliwei static int dw_mci_hi3660_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
368361c7fe9Sliwei {
369361c7fe9Sliwei int i = 0;
370361c7fe9Sliwei struct dw_mci *host = slot->host;
371361c7fe9Sliwei struct mmc_host *mmc = slot->mmc;
372361c7fe9Sliwei int smpl_phase = 0;
373361c7fe9Sliwei u32 tuning_sample_flag = 0;
374361c7fe9Sliwei int best_clksmpl = 0;
375361c7fe9Sliwei
376361c7fe9Sliwei for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) {
377361c7fe9Sliwei smpl_phase %= 32;
378361c7fe9Sliwei
379361c7fe9Sliwei mci_writel(host, TMOUT, ~0);
380361c7fe9Sliwei dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
381361c7fe9Sliwei
382361c7fe9Sliwei if (!mmc_send_tuning(mmc, opcode, NULL))
383361c7fe9Sliwei tuning_sample_flag |= (1 << smpl_phase);
384361c7fe9Sliwei else
385361c7fe9Sliwei tuning_sample_flag &= ~(1 << smpl_phase);
386361c7fe9Sliwei }
387361c7fe9Sliwei
388361c7fe9Sliwei best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag);
389361c7fe9Sliwei if (best_clksmpl < 0) {
390361c7fe9Sliwei dev_err(host->dev, "All phases bad!\n");
391361c7fe9Sliwei return -EIO;
392361c7fe9Sliwei }
393361c7fe9Sliwei
394361c7fe9Sliwei dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl);
395361c7fe9Sliwei
396361c7fe9Sliwei dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n",
397361c7fe9Sliwei best_clksmpl, tuning_sample_flag);
398361c7fe9Sliwei return 0;
399361c7fe9Sliwei }
400361c7fe9Sliwei
dw_mci_hi3660_switch_voltage(struct mmc_host * mmc,struct mmc_ios * ios)401361c7fe9Sliwei static int dw_mci_hi3660_switch_voltage(struct mmc_host *mmc,
402361c7fe9Sliwei struct mmc_ios *ios)
403361c7fe9Sliwei {
404361c7fe9Sliwei int ret = 0;
405361c7fe9Sliwei struct dw_mci_slot *slot = mmc_priv(mmc);
406361c7fe9Sliwei struct k3_priv *priv;
407361c7fe9Sliwei struct dw_mci *host;
408361c7fe9Sliwei
409361c7fe9Sliwei host = slot->host;
410361c7fe9Sliwei priv = host->priv;
411361c7fe9Sliwei
412361c7fe9Sliwei if (!priv || !priv->reg)
413361c7fe9Sliwei return 0;
414361c7fe9Sliwei
415361c7fe9Sliwei if (priv->ctrl_id == DWMMC_SDIO_ID)
416361c7fe9Sliwei return 0;
417361c7fe9Sliwei
418361c7fe9Sliwei if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
419361c7fe9Sliwei ret = dw_mci_set_sel18(host, 0);
420361c7fe9Sliwei else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
421361c7fe9Sliwei ret = dw_mci_set_sel18(host, 1);
422361c7fe9Sliwei if (ret)
423361c7fe9Sliwei return ret;
424361c7fe9Sliwei
425361c7fe9Sliwei if (!IS_ERR(mmc->supply.vqmmc)) {
426361c7fe9Sliwei ret = mmc_regulator_set_vqmmc(mmc, ios);
4279cbe0fc8SMarek Vasut if (ret < 0) {
428361c7fe9Sliwei dev_err(host->dev, "Regulator set error %d\n", ret);
429361c7fe9Sliwei return ret;
430361c7fe9Sliwei }
431361c7fe9Sliwei }
432361c7fe9Sliwei
433361c7fe9Sliwei return 0;
434361c7fe9Sliwei }
435361c7fe9Sliwei
436361c7fe9Sliwei static const struct dw_mci_drv_data hi3660_data = {
437361c7fe9Sliwei .init = dw_mci_hi3660_init,
438361c7fe9Sliwei .set_ios = dw_mci_hi3660_set_ios,
439361c7fe9Sliwei .parse_dt = dw_mci_hi6220_parse_dt,
440361c7fe9Sliwei .execute_tuning = dw_mci_hi3660_execute_tuning,
441361c7fe9Sliwei .switch_voltage = dw_mci_hi3660_switch_voltage,
442361c7fe9Sliwei };
443361c7fe9Sliwei
444036f29d5SZhangfei Gao static const struct of_device_id dw_mci_k3_match[] = {
445361c7fe9Sliwei { .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, },
446036f29d5SZhangfei Gao { .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
4470293efddSZhangfei Gao { .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
448036f29d5SZhangfei Gao {},
449036f29d5SZhangfei Gao };
450036f29d5SZhangfei Gao MODULE_DEVICE_TABLE(of, dw_mci_k3_match);
451036f29d5SZhangfei Gao
dw_mci_k3_probe(struct platform_device * pdev)452036f29d5SZhangfei Gao static int dw_mci_k3_probe(struct platform_device *pdev)
453036f29d5SZhangfei Gao {
454036f29d5SZhangfei Gao const struct dw_mci_drv_data *drv_data;
455036f29d5SZhangfei Gao const struct of_device_id *match;
456036f29d5SZhangfei Gao
457036f29d5SZhangfei Gao match = of_match_node(dw_mci_k3_match, pdev->dev.of_node);
458036f29d5SZhangfei Gao drv_data = match->data;
459036f29d5SZhangfei Gao
460036f29d5SZhangfei Gao return dw_mci_pltfm_register(pdev, drv_data);
461036f29d5SZhangfei Gao }
462036f29d5SZhangfei Gao
4632c8ae20eSShawn Lin static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = {
4642c8ae20eSShawn Lin SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4652c8ae20eSShawn Lin pm_runtime_force_resume)
4662c8ae20eSShawn Lin SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
4672c8ae20eSShawn Lin dw_mci_runtime_resume,
4682c8ae20eSShawn Lin NULL)
4692c8ae20eSShawn Lin };
470036f29d5SZhangfei Gao
471036f29d5SZhangfei Gao static struct platform_driver dw_mci_k3_pltfm_driver = {
472036f29d5SZhangfei Gao .probe = dw_mci_k3_probe,
473*982fe2e0SUwe Kleine-König .remove_new = dw_mci_pltfm_remove,
474036f29d5SZhangfei Gao .driver = {
475036f29d5SZhangfei Gao .name = "dwmmc_k3",
47621b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
477036f29d5SZhangfei Gao .of_match_table = dw_mci_k3_match,
4782c8ae20eSShawn Lin .pm = &dw_mci_k3_dev_pm_ops,
479036f29d5SZhangfei Gao },
480036f29d5SZhangfei Gao };
481036f29d5SZhangfei Gao
482036f29d5SZhangfei Gao module_platform_driver(dw_mci_k3_pltfm_driver);
483036f29d5SZhangfei Gao
484036f29d5SZhangfei Gao MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension");
485036f29d5SZhangfei Gao MODULE_LICENSE("GPL v2");
4867026fd66SZhangfei Gao MODULE_ALIAS("platform:dwmmc_k3");
487