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/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c60 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
62 #define BASE(seg) BASE_INNER(seg) argument
H A Dhw_translate_dcn30.c55 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
57 #define BASE(seg) BASE_INNER(seg) argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
55 #define BASE(seg) BASE_INNER(seg) argument
H A Dhw_translate_dcn20.c50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
52 #define BASE(seg) BASE_INNER(seg) argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
55 #define BASE(seg) BASE_INNER(seg) argument
H A Dhw_translate_dcn32.c48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
50 #define BASE(seg) BASE_INNER(seg) argument
/openbmc/linux/net/caif/
H A Dcfrfml.c216 u8 seg; in cfrfml_transmit() local
241 seg = 1; in cfrfml_transmit()
244 if (cfpkt_add_head(frontpkt, &seg, 1) < 0) in cfrfml_transmit()
273 seg = 0; in cfrfml_transmit()
276 if (cfpkt_add_head(frontpkt, &seg, 1) < 0) in cfrfml_transmit()
/openbmc/linux/arch/x86/pci/
H A Dce4100.c263 static int ce4100_conf_read(unsigned int seg, unsigned int bus, in ce4100_conf_read() argument
266 WARN_ON(seg); in ce4100_conf_read()
275 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); in ce4100_conf_read()
297 static int ce4100_conf_write(unsigned int seg, unsigned int bus, in ce4100_conf_write() argument
300 WARN_ON(seg); in ce4100_conf_write()
310 return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); in ce4100_conf_write()
H A Dpcbios.c183 static int pci_bios_read(unsigned int seg, unsigned int bus, in pci_bios_read() argument
191 WARN_ON(seg); in pci_bios_read()
233 static int pci_bios_write(unsigned int seg, unsigned int bus, in pci_bios_write() argument
241 WARN_ON(seg); in pci_bios_write()
/openbmc/linux/include/linux/
H A Dpeci-cpu.h34 int peci_ep_pci_local_read(struct peci_device *device, u8 seg,
37 int peci_mmio_read(struct peci_device *device, u8 bar, u8 seg,
/openbmc/linux/drivers/scsi/
H A Dxen-scsifront.c221 ring_req->seg[i] = shadow->seg[i]; in scsifront_do_request()
482 struct scsiif_request_segment *seg; in map_data_for_request() local
502 seg = shadow->sg ? : shadow->seg; in map_data_for_request()
514 page = virt_to_page(seg); in map_data_for_request()
515 off = offset_in_page(seg); in map_data_for_request()
527 shadow->seg[ref_cnt].gref = ref; in map_data_for_request()
528 shadow->seg[ref_cnt].offset = (uint16_t)off; in map_data_for_request()
563 seg->gref = ref; in map_data_for_request()
564 seg->offset = (uint16_t)off; in map_data_for_request()
565 seg->length = (uint16_t)bytes; in map_data_for_request()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_translate_dcn21.c50 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg argument
52 #define BASE(seg) BASE_INNER(seg) argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_translate_dcn315.c50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
52 #define BASE(seg) BASE_INNER(seg) argument
/openbmc/linux/drivers/infiniband/hw/mlx5/
H A Dumr.c242 void *cur_edge, *seg; in mlx5r_umr_post_send() local
252 err = mlx5r_begin_wqe(qp, &seg, &ctrl, &idx, &size, &cur_edge, 0, in mlx5r_umr_post_send()
262 mlx5r_finish_wqe(qp, ctrl, seg, size, cur_edge, idx, id.wr_id, 0, in mlx5r_umr_post_send()
380 struct mlx5_mkey_seg *seg, in mlx5r_umr_set_access_flags() argument
387 MLX5_SET(mkc, seg, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); in mlx5r_umr_set_access_flags()
388 MLX5_SET(mkc, seg, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); in mlx5r_umr_set_access_flags()
389 MLX5_SET(mkc, seg, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); in mlx5r_umr_set_access_flags()
390 MLX5_SET(mkc, seg, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); in mlx5r_umr_set_access_flags()
391 MLX5_SET(mkc, seg, lr, 1); in mlx5r_umr_set_access_flags()
392 MLX5_SET(mkc, seg, relaxed_ordering_write, in mlx5r_umr_set_access_flags()
[all …]
/openbmc/openbmc-build-scripts/config/lib/
H A Dignore-filter40 for seg in itertools.accumulate(
43 if any(fnmatch.fnmatch(seg, i) for i in ignore_patterns):
/openbmc/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_av1_req_lat_if.c482 struct vdec_av1_slice_seg seg; member
716 struct mtk_vcodec_mem seg[AV1_MAX_FRAME_BUF_COUNT]; member
980 if (instance->seg[i].va) in vdec_av1_slice_alloc_working_buffer()
981 mtk_vcodec_mem_free(ctx, &instance->seg[i]); in vdec_av1_slice_alloc_working_buffer()
982 instance->seg[i].size = max_sb_w * max_sb_h * 512; in vdec_av1_slice_alloc_working_buffer()
983 ret = mtk_vcodec_mem_alloc(ctx, &instance->seg[i]); in vdec_av1_slice_alloc_working_buffer()
1028 for (i = 0; i < ARRAY_SIZE(instance->seg); i++) in vdec_av1_slice_free_working_buffer()
1029 mtk_vcodec_mem_free(ctx, &instance->seg[i]); in vdec_av1_slice_free_working_buffer()
1184 struct vdec_av1_slice_seg *seg = &uh->seg; in vdec_av1_slice_get_qindex() local
1188 if (seg->segmentation_enabled && in vdec_av1_slice_get_qindex()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c92 #define BASE_INNER(seg) \ argument
93 DCE_BASE__INST0_SEG ## seg
95 #define BASE(seg) \ argument
96 BASE_INNER(seg)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c49 #define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg argument
51 #define BASE(seg) BASE_INNER(seg) argument
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi.h116 #define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) argument
173 #define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) argument
/openbmc/linux/drivers/usb/host/
H A Dxhci-ring.c74 if (!seg || !trb || trb < seg->trbs) in xhci_trb_virt_to_dma()
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); in last_trb_on_ring()
148 *seg = (*seg)->next; in next_trb()
149 *trb = ((*seg)->trbs); in next_trb()
343 seg = ring->enq_seg; in xhci_ring_expansion_needed()
346 seg = seg->next; in xhci_ring_expansion_needed()
827 seg->bounce_len, seg->bounce_offs); in xhci_unmap_td_bounce_buffer()
832 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf, in xhci_unmap_td_bounce_buffer()
835 seg->bounce_len = 0; in xhci_unmap_td_bounce_buffer()
3607 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, in xhci_align_td()
[all …]
/openbmc/phosphor-host-postd/
H A Dmeson.options30 '7seg', type: 'feature', description: 'Enable building 7seg POST daemon.',
/openbmc/linux/tools/lib/bpf/
H A Dlibbpf_internal.h408 #define for_each_btf_ext_sec(seg, sec) \ argument
409 for (sec = (seg)->info; \
410 (void *)sec < (seg)->info + (seg)->len; \
412 (seg)->rec_size * sec->num_info)
414 #define for_each_btf_ext_rec(seg, sec, i, rec) \ argument
417 i++, rec = (void *)rec + (seg)->rec_size)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c44 #define BASE_INNER(seg) \ argument
45 DCE_BASE__INST0_SEG ## seg
48 #define BASE(seg) \ argument
49 BASE_INNER(seg)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c44 #define BASE_INNER(seg) \ argument
45 DCE_BASE__INST0_SEG ## seg
48 #define BASE(seg) \ argument
49 BASE_INNER(seg)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c109 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg argument
112 #define BASE(seg) BASE_INNER(seg) argument

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