1*b9d7eb6aSQingqing Zhuo /*
2*b9d7eb6aSQingqing Zhuo * Copyright 2021 Advanced Micro Devices, Inc.
3*b9d7eb6aSQingqing Zhuo *
4*b9d7eb6aSQingqing Zhuo * Permission is hereby granted, free of charge, to any person obtaining a
5*b9d7eb6aSQingqing Zhuo * copy of this software and associated documentation files (the "Software"),
6*b9d7eb6aSQingqing Zhuo * to deal in the Software without restriction, including without limitation
7*b9d7eb6aSQingqing Zhuo * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b9d7eb6aSQingqing Zhuo * and/or sell copies of the Software, and to permit persons to whom the
9*b9d7eb6aSQingqing Zhuo * Software is furnished to do so, subject to the following conditions:
10*b9d7eb6aSQingqing Zhuo *
11*b9d7eb6aSQingqing Zhuo * The above copyright notice and this permission notice shall be included in
12*b9d7eb6aSQingqing Zhuo * all copies or substantial portions of the Software.
13*b9d7eb6aSQingqing Zhuo *
14*b9d7eb6aSQingqing Zhuo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b9d7eb6aSQingqing Zhuo * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b9d7eb6aSQingqing Zhuo * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b9d7eb6aSQingqing Zhuo * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b9d7eb6aSQingqing Zhuo * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b9d7eb6aSQingqing Zhuo * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b9d7eb6aSQingqing Zhuo * OTHER DEALINGS IN THE SOFTWARE.
21*b9d7eb6aSQingqing Zhuo *
22*b9d7eb6aSQingqing Zhuo * Authors: AMD
23*b9d7eb6aSQingqing Zhuo *
24*b9d7eb6aSQingqing Zhuo */
25*b9d7eb6aSQingqing Zhuo
26*b9d7eb6aSQingqing Zhuo #include "hw_translate_dcn315.h"
27*b9d7eb6aSQingqing Zhuo
28*b9d7eb6aSQingqing Zhuo #include "dm_services.h"
29*b9d7eb6aSQingqing Zhuo #include "include/gpio_types.h"
30*b9d7eb6aSQingqing Zhuo #include "../hw_translate.h"
31*b9d7eb6aSQingqing Zhuo
32*b9d7eb6aSQingqing Zhuo #include "dcn/dcn_3_1_5_offset.h"
33*b9d7eb6aSQingqing Zhuo #include "dcn/dcn_3_1_5_sh_mask.h"
34*b9d7eb6aSQingqing Zhuo
35*b9d7eb6aSQingqing Zhuo /* begin *********************
36*b9d7eb6aSQingqing Zhuo * macros to expend register list macro defined in HW object header file */
37*b9d7eb6aSQingqing Zhuo
38*b9d7eb6aSQingqing Zhuo #define DCN_BASE__INST0_SEG0 0x00000012
39*b9d7eb6aSQingqing Zhuo #define DCN_BASE__INST0_SEG1 0x000000C0
40*b9d7eb6aSQingqing Zhuo #define DCN_BASE__INST0_SEG2 0x000034C0
41*b9d7eb6aSQingqing Zhuo #define DCN_BASE__INST0_SEG3 0x00009000
42*b9d7eb6aSQingqing Zhuo #define DCN_BASE__INST0_SEG4 0x02403C00
43*b9d7eb6aSQingqing Zhuo #define DCN_BASE__INST0_SEG5 0
44*b9d7eb6aSQingqing Zhuo
45*b9d7eb6aSQingqing Zhuo /* DCN */
46*b9d7eb6aSQingqing Zhuo #define block HPD
47*b9d7eb6aSQingqing Zhuo #define reg_num 0
48*b9d7eb6aSQingqing Zhuo
49*b9d7eb6aSQingqing Zhuo #undef BASE_INNER
50*b9d7eb6aSQingqing Zhuo #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
51*b9d7eb6aSQingqing Zhuo
52*b9d7eb6aSQingqing Zhuo #define BASE(seg) BASE_INNER(seg)
53*b9d7eb6aSQingqing Zhuo
54*b9d7eb6aSQingqing Zhuo #undef REG
55*b9d7eb6aSQingqing Zhuo #define REG(reg_name)\
56*b9d7eb6aSQingqing Zhuo BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
57*b9d7eb6aSQingqing Zhuo #define SF_HPD(reg_name, field_name, post_fix)\
58*b9d7eb6aSQingqing Zhuo .field_name = reg_name ## __ ## field_name ## post_fix
59*b9d7eb6aSQingqing Zhuo
60*b9d7eb6aSQingqing Zhuo
61*b9d7eb6aSQingqing Zhuo /* macros to expend register list macro defined in HW object header file
62*b9d7eb6aSQingqing Zhuo * end *********************/
63*b9d7eb6aSQingqing Zhuo
64*b9d7eb6aSQingqing Zhuo
offset_to_id(uint32_t offset,uint32_t mask,enum gpio_id * id,uint32_t * en)65*b9d7eb6aSQingqing Zhuo static bool offset_to_id(
66*b9d7eb6aSQingqing Zhuo uint32_t offset,
67*b9d7eb6aSQingqing Zhuo uint32_t mask,
68*b9d7eb6aSQingqing Zhuo enum gpio_id *id,
69*b9d7eb6aSQingqing Zhuo uint32_t *en)
70*b9d7eb6aSQingqing Zhuo {
71*b9d7eb6aSQingqing Zhuo switch (offset) {
72*b9d7eb6aSQingqing Zhuo /* GENERIC */
73*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_GENERIC_A):
74*b9d7eb6aSQingqing Zhuo *id = GPIO_ID_GENERIC;
75*b9d7eb6aSQingqing Zhuo switch (mask) {
76*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
77*b9d7eb6aSQingqing Zhuo *en = GPIO_GENERIC_A;
78*b9d7eb6aSQingqing Zhuo return true;
79*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
80*b9d7eb6aSQingqing Zhuo *en = GPIO_GENERIC_B;
81*b9d7eb6aSQingqing Zhuo return true;
82*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
83*b9d7eb6aSQingqing Zhuo *en = GPIO_GENERIC_C;
84*b9d7eb6aSQingqing Zhuo return true;
85*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
86*b9d7eb6aSQingqing Zhuo *en = GPIO_GENERIC_D;
87*b9d7eb6aSQingqing Zhuo return true;
88*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
89*b9d7eb6aSQingqing Zhuo *en = GPIO_GENERIC_E;
90*b9d7eb6aSQingqing Zhuo return true;
91*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
92*b9d7eb6aSQingqing Zhuo *en = GPIO_GENERIC_F;
93*b9d7eb6aSQingqing Zhuo return true;
94*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
95*b9d7eb6aSQingqing Zhuo *en = GPIO_GENERIC_G;
96*b9d7eb6aSQingqing Zhuo return true;
97*b9d7eb6aSQingqing Zhuo default:
98*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
99*b9d7eb6aSQingqing Zhuo return false;
100*b9d7eb6aSQingqing Zhuo }
101*b9d7eb6aSQingqing Zhuo break;
102*b9d7eb6aSQingqing Zhuo /* HPD */
103*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_HPD_A):
104*b9d7eb6aSQingqing Zhuo *id = GPIO_ID_HPD;
105*b9d7eb6aSQingqing Zhuo switch (mask) {
106*b9d7eb6aSQingqing Zhuo case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
107*b9d7eb6aSQingqing Zhuo *en = GPIO_HPD_1;
108*b9d7eb6aSQingqing Zhuo return true;
109*b9d7eb6aSQingqing Zhuo case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
110*b9d7eb6aSQingqing Zhuo *en = GPIO_HPD_2;
111*b9d7eb6aSQingqing Zhuo return true;
112*b9d7eb6aSQingqing Zhuo case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
113*b9d7eb6aSQingqing Zhuo *en = GPIO_HPD_3;
114*b9d7eb6aSQingqing Zhuo return true;
115*b9d7eb6aSQingqing Zhuo case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
116*b9d7eb6aSQingqing Zhuo *en = GPIO_HPD_4;
117*b9d7eb6aSQingqing Zhuo return true;
118*b9d7eb6aSQingqing Zhuo case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
119*b9d7eb6aSQingqing Zhuo *en = GPIO_HPD_5;
120*b9d7eb6aSQingqing Zhuo return true;
121*b9d7eb6aSQingqing Zhuo case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
122*b9d7eb6aSQingqing Zhuo *en = GPIO_HPD_6;
123*b9d7eb6aSQingqing Zhuo return true;
124*b9d7eb6aSQingqing Zhuo default:
125*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
126*b9d7eb6aSQingqing Zhuo return false;
127*b9d7eb6aSQingqing Zhuo }
128*b9d7eb6aSQingqing Zhuo break;
129*b9d7eb6aSQingqing Zhuo /* REG(DC_GPIO_GENLK_MASK */
130*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_GENLK_A):
131*b9d7eb6aSQingqing Zhuo *id = GPIO_ID_GSL;
132*b9d7eb6aSQingqing Zhuo switch (mask) {
133*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
134*b9d7eb6aSQingqing Zhuo *en = GPIO_GSL_GENLOCK_CLOCK;
135*b9d7eb6aSQingqing Zhuo return true;
136*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
137*b9d7eb6aSQingqing Zhuo *en = GPIO_GSL_GENLOCK_VSYNC;
138*b9d7eb6aSQingqing Zhuo return true;
139*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
140*b9d7eb6aSQingqing Zhuo *en = GPIO_GSL_SWAPLOCK_A;
141*b9d7eb6aSQingqing Zhuo return true;
142*b9d7eb6aSQingqing Zhuo case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
143*b9d7eb6aSQingqing Zhuo *en = GPIO_GSL_SWAPLOCK_B;
144*b9d7eb6aSQingqing Zhuo return true;
145*b9d7eb6aSQingqing Zhuo default:
146*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
147*b9d7eb6aSQingqing Zhuo return false;
148*b9d7eb6aSQingqing Zhuo }
149*b9d7eb6aSQingqing Zhuo break;
150*b9d7eb6aSQingqing Zhuo /* DDC */
151*b9d7eb6aSQingqing Zhuo /* we don't care about the GPIO_ID for DDC
152*b9d7eb6aSQingqing Zhuo * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
153*b9d7eb6aSQingqing Zhuo * directly in the create method
154*b9d7eb6aSQingqing Zhuo */
155*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_DDC1_A):
156*b9d7eb6aSQingqing Zhuo *en = GPIO_DDC_LINE_DDC1;
157*b9d7eb6aSQingqing Zhuo return true;
158*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_DDC2_A):
159*b9d7eb6aSQingqing Zhuo *en = GPIO_DDC_LINE_DDC2;
160*b9d7eb6aSQingqing Zhuo return true;
161*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_DDC3_A):
162*b9d7eb6aSQingqing Zhuo *en = GPIO_DDC_LINE_DDC3;
163*b9d7eb6aSQingqing Zhuo return true;
164*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_DDC4_A):
165*b9d7eb6aSQingqing Zhuo *en = GPIO_DDC_LINE_DDC4;
166*b9d7eb6aSQingqing Zhuo return true;
167*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_DDC5_A):
168*b9d7eb6aSQingqing Zhuo *en = GPIO_DDC_LINE_DDC5;
169*b9d7eb6aSQingqing Zhuo return true;
170*b9d7eb6aSQingqing Zhuo case REG(DC_GPIO_DDCVGA_A):
171*b9d7eb6aSQingqing Zhuo *en = GPIO_DDC_LINE_DDC_VGA;
172*b9d7eb6aSQingqing Zhuo return true;
173*b9d7eb6aSQingqing Zhuo
174*b9d7eb6aSQingqing Zhuo /*
175*b9d7eb6aSQingqing Zhuo * case REG(DC_GPIO_I2CPAD_A): not exit
176*b9d7eb6aSQingqing Zhuo * case REG(DC_GPIO_PWRSEQ_A):
177*b9d7eb6aSQingqing Zhuo * case REG(DC_GPIO_PAD_STRENGTH_1):
178*b9d7eb6aSQingqing Zhuo * case REG(DC_GPIO_PAD_STRENGTH_2):
179*b9d7eb6aSQingqing Zhuo * case REG(DC_GPIO_DEBUG):
180*b9d7eb6aSQingqing Zhuo */
181*b9d7eb6aSQingqing Zhuo /* UNEXPECTED */
182*b9d7eb6aSQingqing Zhuo default:
183*b9d7eb6aSQingqing Zhuo /* case REG(DC_GPIO_SYNCA_A): not exist */
184*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
185*b9d7eb6aSQingqing Zhuo return false;
186*b9d7eb6aSQingqing Zhuo }
187*b9d7eb6aSQingqing Zhuo }
188*b9d7eb6aSQingqing Zhuo
id_to_offset(enum gpio_id id,uint32_t en,struct gpio_pin_info * info)189*b9d7eb6aSQingqing Zhuo static bool id_to_offset(
190*b9d7eb6aSQingqing Zhuo enum gpio_id id,
191*b9d7eb6aSQingqing Zhuo uint32_t en,
192*b9d7eb6aSQingqing Zhuo struct gpio_pin_info *info)
193*b9d7eb6aSQingqing Zhuo {
194*b9d7eb6aSQingqing Zhuo bool result = true;
195*b9d7eb6aSQingqing Zhuo
196*b9d7eb6aSQingqing Zhuo switch (id) {
197*b9d7eb6aSQingqing Zhuo case GPIO_ID_DDC_DATA:
198*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;
199*b9d7eb6aSQingqing Zhuo switch (en) {
200*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC1:
201*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC1_A);
202*b9d7eb6aSQingqing Zhuo break;
203*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC2:
204*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC2_A);
205*b9d7eb6aSQingqing Zhuo break;
206*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC3:
207*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC3_A);
208*b9d7eb6aSQingqing Zhuo break;
209*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC4:
210*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC4_A);
211*b9d7eb6aSQingqing Zhuo break;
212*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC5:
213*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC5_A);
214*b9d7eb6aSQingqing Zhuo break;
215*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC_VGA:
216*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDCVGA_A);
217*b9d7eb6aSQingqing Zhuo break;
218*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_I2C_PAD:
219*b9d7eb6aSQingqing Zhuo default:
220*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
221*b9d7eb6aSQingqing Zhuo result = false;
222*b9d7eb6aSQingqing Zhuo }
223*b9d7eb6aSQingqing Zhuo break;
224*b9d7eb6aSQingqing Zhuo case GPIO_ID_DDC_CLOCK:
225*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;
226*b9d7eb6aSQingqing Zhuo switch (en) {
227*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC1:
228*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC1_A);
229*b9d7eb6aSQingqing Zhuo break;
230*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC2:
231*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC2_A);
232*b9d7eb6aSQingqing Zhuo break;
233*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC3:
234*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC3_A);
235*b9d7eb6aSQingqing Zhuo break;
236*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC4:
237*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC4_A);
238*b9d7eb6aSQingqing Zhuo break;
239*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC5:
240*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDC5_A);
241*b9d7eb6aSQingqing Zhuo break;
242*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_DDC_VGA:
243*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_DDCVGA_A);
244*b9d7eb6aSQingqing Zhuo break;
245*b9d7eb6aSQingqing Zhuo case GPIO_DDC_LINE_I2C_PAD:
246*b9d7eb6aSQingqing Zhuo default:
247*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
248*b9d7eb6aSQingqing Zhuo result = false;
249*b9d7eb6aSQingqing Zhuo }
250*b9d7eb6aSQingqing Zhuo break;
251*b9d7eb6aSQingqing Zhuo case GPIO_ID_GENERIC:
252*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_GENERIC_A);
253*b9d7eb6aSQingqing Zhuo switch (en) {
254*b9d7eb6aSQingqing Zhuo case GPIO_GENERIC_A:
255*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
256*b9d7eb6aSQingqing Zhuo break;
257*b9d7eb6aSQingqing Zhuo case GPIO_GENERIC_B:
258*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
259*b9d7eb6aSQingqing Zhuo break;
260*b9d7eb6aSQingqing Zhuo case GPIO_GENERIC_C:
261*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
262*b9d7eb6aSQingqing Zhuo break;
263*b9d7eb6aSQingqing Zhuo case GPIO_GENERIC_D:
264*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
265*b9d7eb6aSQingqing Zhuo break;
266*b9d7eb6aSQingqing Zhuo case GPIO_GENERIC_E:
267*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
268*b9d7eb6aSQingqing Zhuo break;
269*b9d7eb6aSQingqing Zhuo case GPIO_GENERIC_F:
270*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
271*b9d7eb6aSQingqing Zhuo break;
272*b9d7eb6aSQingqing Zhuo case GPIO_GENERIC_G:
273*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
274*b9d7eb6aSQingqing Zhuo break;
275*b9d7eb6aSQingqing Zhuo default:
276*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
277*b9d7eb6aSQingqing Zhuo result = false;
278*b9d7eb6aSQingqing Zhuo }
279*b9d7eb6aSQingqing Zhuo break;
280*b9d7eb6aSQingqing Zhuo case GPIO_ID_HPD:
281*b9d7eb6aSQingqing Zhuo info->offset = REG(DC_GPIO_HPD_A);
282*b9d7eb6aSQingqing Zhuo switch (en) {
283*b9d7eb6aSQingqing Zhuo case GPIO_HPD_1:
284*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
285*b9d7eb6aSQingqing Zhuo break;
286*b9d7eb6aSQingqing Zhuo case GPIO_HPD_2:
287*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
288*b9d7eb6aSQingqing Zhuo break;
289*b9d7eb6aSQingqing Zhuo case GPIO_HPD_3:
290*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
291*b9d7eb6aSQingqing Zhuo break;
292*b9d7eb6aSQingqing Zhuo case GPIO_HPD_4:
293*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
294*b9d7eb6aSQingqing Zhuo break;
295*b9d7eb6aSQingqing Zhuo case GPIO_HPD_5:
296*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
297*b9d7eb6aSQingqing Zhuo break;
298*b9d7eb6aSQingqing Zhuo case GPIO_HPD_6:
299*b9d7eb6aSQingqing Zhuo info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
300*b9d7eb6aSQingqing Zhuo break;
301*b9d7eb6aSQingqing Zhuo default:
302*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
303*b9d7eb6aSQingqing Zhuo result = false;
304*b9d7eb6aSQingqing Zhuo }
305*b9d7eb6aSQingqing Zhuo break;
306*b9d7eb6aSQingqing Zhuo case GPIO_ID_GSL:
307*b9d7eb6aSQingqing Zhuo switch (en) {
308*b9d7eb6aSQingqing Zhuo case GPIO_GSL_GENLOCK_CLOCK:
309*b9d7eb6aSQingqing Zhuo /*not implmented*/
310*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
311*b9d7eb6aSQingqing Zhuo result = false;
312*b9d7eb6aSQingqing Zhuo break;
313*b9d7eb6aSQingqing Zhuo case GPIO_GSL_GENLOCK_VSYNC:
314*b9d7eb6aSQingqing Zhuo /*not implmented*/
315*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
316*b9d7eb6aSQingqing Zhuo result = false;
317*b9d7eb6aSQingqing Zhuo break;
318*b9d7eb6aSQingqing Zhuo case GPIO_GSL_SWAPLOCK_A:
319*b9d7eb6aSQingqing Zhuo /*not implmented*/
320*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
321*b9d7eb6aSQingqing Zhuo result = false;
322*b9d7eb6aSQingqing Zhuo break;
323*b9d7eb6aSQingqing Zhuo case GPIO_GSL_SWAPLOCK_B:
324*b9d7eb6aSQingqing Zhuo /*not implmented*/
325*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
326*b9d7eb6aSQingqing Zhuo result = false;
327*b9d7eb6aSQingqing Zhuo
328*b9d7eb6aSQingqing Zhuo break;
329*b9d7eb6aSQingqing Zhuo default:
330*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
331*b9d7eb6aSQingqing Zhuo result = false;
332*b9d7eb6aSQingqing Zhuo }
333*b9d7eb6aSQingqing Zhuo break;
334*b9d7eb6aSQingqing Zhuo case GPIO_ID_SYNC:
335*b9d7eb6aSQingqing Zhuo case GPIO_ID_VIP_PAD:
336*b9d7eb6aSQingqing Zhuo default:
337*b9d7eb6aSQingqing Zhuo ASSERT_CRITICAL(false);
338*b9d7eb6aSQingqing Zhuo result = false;
339*b9d7eb6aSQingqing Zhuo }
340*b9d7eb6aSQingqing Zhuo
341*b9d7eb6aSQingqing Zhuo if (result) {
342*b9d7eb6aSQingqing Zhuo info->offset_y = info->offset + 2;
343*b9d7eb6aSQingqing Zhuo info->offset_en = info->offset + 1;
344*b9d7eb6aSQingqing Zhuo info->offset_mask = info->offset - 1;
345*b9d7eb6aSQingqing Zhuo
346*b9d7eb6aSQingqing Zhuo info->mask_y = info->mask;
347*b9d7eb6aSQingqing Zhuo info->mask_en = info->mask;
348*b9d7eb6aSQingqing Zhuo info->mask_mask = info->mask;
349*b9d7eb6aSQingqing Zhuo }
350*b9d7eb6aSQingqing Zhuo
351*b9d7eb6aSQingqing Zhuo return result;
352*b9d7eb6aSQingqing Zhuo }
353*b9d7eb6aSQingqing Zhuo
354*b9d7eb6aSQingqing Zhuo /* function table */
355*b9d7eb6aSQingqing Zhuo static const struct hw_translate_funcs funcs = {
356*b9d7eb6aSQingqing Zhuo .offset_to_id = offset_to_id,
357*b9d7eb6aSQingqing Zhuo .id_to_offset = id_to_offset,
358*b9d7eb6aSQingqing Zhuo };
359*b9d7eb6aSQingqing Zhuo
360*b9d7eb6aSQingqing Zhuo /*
361*b9d7eb6aSQingqing Zhuo * dal_hw_translate_dcn30_init
362*b9d7eb6aSQingqing Zhuo *
363*b9d7eb6aSQingqing Zhuo * @brief
364*b9d7eb6aSQingqing Zhuo * Initialize Hw translate function pointers.
365*b9d7eb6aSQingqing Zhuo *
366*b9d7eb6aSQingqing Zhuo * @param
367*b9d7eb6aSQingqing Zhuo * struct hw_translate *tr - [out] struct of function pointers
368*b9d7eb6aSQingqing Zhuo *
369*b9d7eb6aSQingqing Zhuo */
dal_hw_translate_dcn315_init(struct hw_translate * tr)370*b9d7eb6aSQingqing Zhuo void dal_hw_translate_dcn315_init(struct hw_translate *tr)
371*b9d7eb6aSQingqing Zhuo {
372*b9d7eb6aSQingqing Zhuo tr->funcs = &funcs;
373*b9d7eb6aSQingqing Zhuo }
374*b9d7eb6aSQingqing Zhuo
375