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Searched refs:registers (Results 51 – 75 of 2013) sorted by relevance

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/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Dfeature-arm-neon.inc10 TUNEVALID[vfpv3d16] = "Enable Vector Floating Point Version 3 with 16 registers (vfpv3-d16) unit."
13 TUNEVALID[vfpv3] = "Enable Vector Floating Point Version 3 with 32 registers (vfpv3) unit."
20 TUNEVALID[vfpv4d16] = "Enable Vector Floating Point Version 4 with 16 registers (vfpv4-d16) unit."
23 …6] = "Enable Vector Floating Point Version 5, Single Precision. with 16 registers (fpv5-sp-d16) un…
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxgene-pci-msi.txt9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
53 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
H A Dmobiveil-pcie.txt12 - reg: Should contain PCIe registers location and length
14 "config_axi_slave": PCIe controller registers
15 "csr_axi_slave" : Bridge config registers
17 "gpio_slave" : GPIO registers to control slot power
18 "apb_csr" : MSI registers
H A Dsnps,dw-pcie.yaml61 Shadow DWC PCIe config-space registers. This space is selected
63 the PCI-SIG PCIe CFG-space with the shadow registers for some
66 but still there are some shadow registers available for the
70 External Local Bus registers. It's an application-dependent
71 registers normally defined by the platform engineers. The space
77 iATU/eDMA registers common for all device functions. It's an
87 Platform-specific eDMA registers. Some platforms may have eDMA
94 PHY/PCS configuration registers. Some platforms can have the
96 region, but mainly these registers are indirectly accessible
136 from/to the VPD capability registers.
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/openbmc/qemu/docs/specs/
H A Dstandard-vga.rst80 port first), so indexed registers can be updated with a single
83 bochs dispi interface registers, mapped flat without index/data ports.
86 QEMU extended registers. QEMU 2.2+ only.
87 The pci revision is 2 (or greater) when these registers are present.
88 The registers are 32bit.
/openbmc/u-boot/drivers/pinctrl/nxp/
H A DKconfig19 property and configure related registers.
33 property and configure related registers.
47 property and configure related registers.
61 registers.
76 registers.
90 registers.
104 property and configure related registers.
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Ddevlink.c272 u16 *registers; in mv88e6xxx_region_global_snapshot() local
275 registers = kmalloc_array(32, sizeof(u16), GFP_KERNEL); in mv88e6xxx_region_global_snapshot()
276 if (!registers) in mv88e6xxx_region_global_snapshot()
283 err = mv88e6xxx_g1_read(chip, i, &registers[i]); in mv88e6xxx_region_global_snapshot()
286 err = mv88e6xxx_g2_read(chip, i, &registers[i]); in mv88e6xxx_region_global_snapshot()
293 kfree(registers); in mv88e6xxx_region_global_snapshot()
297 *data = (u8 *)registers; in mv88e6xxx_region_global_snapshot()
631 u16 *registers; in mv88e6xxx_region_port_snapshot() local
635 if (!registers) in mv88e6xxx_region_port_snapshot()
642 kfree(registers); in mv88e6xxx_region_port_snapshot()
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/openbmc/linux/drivers/char/xillybus/
H A Dxillybus_core.c147 ep->registers + fpga_msg_ctrl_reg); in xillybus_isr()
803 channel->endpoint->registers + in xillybus_read()
888 channel->endpoint->registers + in xillybus_read()
894 channel->endpoint->registers + in xillybus_read()
983 channel->endpoint->registers + in xillybus_read()
1339 channel->endpoint->registers + in xillybus_write()
1345 channel->endpoint->registers + in xillybus_write()
1523 channel->endpoint->registers + in xillybus_open()
1544 channel->endpoint->registers + in xillybus_open()
1588 channel->endpoint->registers + in xillybus_release()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Ddm816x-phy.txt7 - reg-names : name for the phy registers
10 - syscon: phandle for the syscon node to access misc registers
12 - syscon: phandle for the syscon node to access misc registers
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra186-gpio.txt12 major sets of registers exist:
14 a) Security registers, which allow configuration of allowed access to the GPIO
15 register set. These registers exist in a single contiguous block of physical
19 Access to this set of registers is not necessary in all circumstances. Code
20 that wishes to configure access to the GPIO registers needs access to these
22 need access to these registers.
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
25 controllers, these registers are exposed via multiple "physical aliases" in
37 implemented GPIOs within each port varies. GPIO registers within a controller
75 - "gpio": Mandatory. GPIO control registers. This may cover either:
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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dnvidia,tegra186-gpio.yaml23 block. Two major sets of registers exist:
25 a) Security registers, which allow configuration of allowed access to the
26 GPIO register set. These registers exist in a single contiguous block
30 Access to this set of registers is not necessary in all circumstances.
32 to these registers to do so. Code which simply wishes to read or write
33 GPIO data does not need access to these registers.
35 b) GPIO registers, which allow manipulation of the GPIO signals. In some
36 GPIO controllers, these registers are exposed via multiple "physical
48 of implemented GPIOs within each port varies. GPIO registers within a
97 - description: Security configuration registers.
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
10 set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains
11 a set of I2S_IN registers.
/openbmc/linux/Documentation/devicetree/bindings/mips/lantiq/
H A Drcu.txt5 where each sub-device has its own set of registers.
8 uses one or multiple register exclusively, but for some registers some
10 With this patch all accesses to the RCU registers will go through
18 - reg : The address and length of the system control registers
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dmv-xor-v2.txt7 - reg: Should contain registers location and length (two sets)
8 the first set is the DMA registers
9 the second set is the global registers
/openbmc/linux/Documentation/bpf/standardization/
H A Dabi.rst14 BPF has 10 general purpose registers and a read-only frame pointer register,
21 * R6 - R9: callee saved registers that function calls will preserve
24 R0 - R5 are scratch registers and BPF programs needs to spill/fill them if
/openbmc/linux/drivers/thermal/ti-soc-thermal/
H A Ddra752-thermal-data.c334 .registers = &dra752_mpu_temp_sensor_registers,
343 .registers = &dra752_gpu_temp_sensor_registers,
350 .registers = &dra752_core_temp_sensor_registers,
357 .registers = &dra752_dspeve_temp_sensor_registers,
364 .registers = &dra752_iva_temp_sensor_registers,
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpic-msgr.txt12 the MPIC containing the message registers.
25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
29 be <u32>. If not present, then all of the message registers in the block
50 // Message registers 0 and 2 in this block can receive interrupts on
59 // Message registers 0 and 2 in this block can receive interrupts on
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1046a.dtsi248 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
249 0x00 0x03480000 0x0 0x40000 /* lut registers */
250 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
264 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
265 0x00 0x03580000 0x0 0x40000 /* lut registers */
266 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
281 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
282 0x00 0x03680000 0x0 0x40000 /* lut registers */
283 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-mss-pil.yaml23 - description: MSS QDSP6 registers
24 - description: RMB registers
109 Halt registers are used to halt transactions of various sub-components
113 - description: phandle to TCSR_MUTEX registers
121 description: EXT registers are used for various power related functionality
124 - description: phandle to TCSR_REG registers
128 - description: phandle to TCSR_MUTEX registers
134 description: QACCEPT registers are used to bring up/down Q-channels
137 - description: phandle to TCSR_MUTEX registers
/openbmc/u-boot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt8 - reg: base addresses and lengths of the pcie control and global control registers.
9 "ctrl" registers points to the global control registers, while the "config" space
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
/openbmc/u-boot/doc/
H A DREADME.fsl_iim28 Read operations are implemented as read accesses to the shadow registers,
37 this operation, the shadow registers are reloaded by the hardware (not
39 these registers).
43 registers, as explained in 30.4.5.4.
H A DREADME.fsl-esdhc5 operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC
18 ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
21 ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
/openbmc/linux/arch/arm/include/asm/
H A Dvfpmacros.h30 @ read all the working registers back into the VFP
49 cmp \tmp, #2 @ 32 x 64bit registers?
56 @ write all the working registers out of the VFP
74 cmp \tmp, #2 @ 32 x 64bit registers?
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h57 .registers = _reg, \
64 const u32 *registers; member
131 .registers = _reg, .count = ARRAY_SIZE(_reg) }
137 const u32 *registers; member
172 const u32 *registers; member
179 { .val0 = _base, .val1 = _type, .registers = _array, \
296 { .registers = _array, .count = ARRAY_SIZE(_array), \
H A Dadreno_gpu.c689 if (!adreno_gpu->registers) in adreno_gpu_state_get()
694 count += adreno_gpu->registers[i + 1] - in adreno_gpu_state_get()
695 adreno_gpu->registers[i] + 1; in adreno_gpu_state_get()
698 if (state->registers) { in adreno_gpu_state_get()
702 u32 start = adreno_gpu->registers[i]; in adreno_gpu_state_get()
703 u32 end = adreno_gpu->registers[i + 1]; in adreno_gpu_state_get()
707 state->registers[pos++] = addr; in adreno_gpu_state_get()
731 kfree(state->registers); in adreno_gpu_state_destroy()
894 state->registers[i * 2] << 2, in adreno_show()
895 state->registers[(i * 2) + 1]); in adreno_show()
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