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Searched refs:p15 (Results 51 – 75 of 156) sorted by relevance

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/openbmc/linux/arch/arm/mm/
H A Dtlb-v7.S49 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
51 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
53 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
80 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
82 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
H A Dproc-v7-2level.S49 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
56 mcr p15, 0, r1, c13, c0, 1 @ set context ID
58 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
106 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
147 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
152 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
H A Dcache-v4.S40 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
59 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
115 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
H A Dabort-ev6.S22 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR
29 mrc p15, 0, r3, c0, c0, 0 @ get processor id
H A Dproc-v7-3level.S50 mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
87 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
131 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
135 mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead-sa1100.S23 mrc p15, 0, r0, c1, c0, 0 @ read control reg
37 mcr p15, 0, r0, c7, c10, 4 @ drain WB
38 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
41 mrc p15, 0, r0, c1, c0, 0 @ read control reg
44 mcr p15, 0, r0, c1, c0, 0
H A Dhead-xscale.S27 mcr p15, 0, r0, c7, c10, 4 @ drain WB
28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
31 mrc p15, 0, r0, c1, c0, 0 @ read control reg
34 mcr p15, 0, r0, c1, c0, 0
/openbmc/u-boot/arch/arm/cpu/arm946es/
H A Dstart.S79 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
80 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
85 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
/openbmc/u-boot/arch/arm/cpu/arm1136/
H A Dstart.S71 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
72 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
77 mrc p15, 0, r0, c1, c0, 0
82 mcr p15, 0, r0, c1, c0, 0
/openbmc/u-boot/arch/arm/cpu/arm1176/
H A Dstart.S77 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
78 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
83 mrc p15, 0, r0, c1, c0, 0
97 mcr p15, 0, r0, c1, c0, 0
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dpsci.S158 mrc p15, 0, r7, c1, c1, 0
160 mcr p15, 0, r4, c1, c1, 0
176 2: mcr p15, 0, r7, c1, c1, 0
183 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
240 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
242 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
250 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
252 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
265 mrc p15, 0, r0, c1, c0, 0 @ SCTLR
[all …]
H A Dcache_v7_asm.S27 mrc p15, 1, r0, c0, c0, 1 @ read clidr
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
41 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
58 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
98 mrc p15, 1, r0, c0, c0, 1 @ read clidr
109 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
111 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
128 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
139 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
/openbmc/u-boot/arch/arm/cpu/arm920t/
H A Dstart.S87 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
88 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
93 mrc p15, 0, r0, c1, c0, 0
98 mcr p15, 0, r0, c1, c0, 0
/openbmc/u-boot/arch/arm/cpu/sa1100/
H A Dstart.S112 mrc p15,0,r0,c1,c0
117 mcr p15,0,r0,c1,c0
123 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
124 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/openbmc/linux/arch/arm/mach-spear/
H A Dheadsmp.S21 mrc p15, 0, r0, c0, c0, 5
32 mrc p15, 0, r0, c1, c0, 1
34 mcr p15, 0, r0, c1, c0, 1
/openbmc/linux/arch/arm/mach-tegra/
H A Dsleep.h70 mrc p15, 0, \rd, c0, c0, 5
82 mrc p15, 0, \tmp1, c0, c0, 0
90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
96 mrceq p15, 0, \tmp1, c0, c0, 5
H A Dreset-handler.S157 mrc p15, 0, r0, c1, c0, 0 @ read system control register
159 mcr p15, 0, r0, c1, c0, 0 @ write system control register
160 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
163 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
173 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
176 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
181 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
/openbmc/linux/arch/arm/mach-socfpga/
H A Dself-refresh.S49 mrc p15, 0, r2, c15, c0, 0
51 mcr p15, 0, r2, c15, c0, 0
116 mrc p15, 0, r2, c15, c0, 0
118 mcr p15, 0, r2, c15, c0, 0
/openbmc/u-boot/arch/arm/mach-mediatek/mt7629/
H A Dlowlevel_init.S28 mcr p15, 0, r0, c14, c0, 0
31 mrc p15, 0, r0, c1, c0, 1
33 mcr p15, 0, r0, c1, c0, 1
36 mrc p15, 0, r0, c0, c0, 5
/openbmc/linux/arch/arm/mach-mvebu/
H A Dpmsu_ll.S14 mrc p15, 4, r1, c15, c0 @ get SCU base address
16 mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
35 mrc p15, 0, r1, c1, c0, 0
37 mcr p15, 0, r1, c1, c0, 0
/openbmc/linux/arch/arm/mach-omap2/
H A Domap-headsmp.S46 mrc p15, 0, r4, c0, c0, 5
64 mrc p15, 0, r4, c0, c0, 5
86 mrc p15, 0, r4, c0, c0, 5
103 mrc p15, 0, r4, c0, c0, 5
/openbmc/linux/arch/arm/kernel/
H A Diwmmxt.S72 mrc p15, 0, r2, c15, c1, 0
78 mcr p15, 0, r2, c15, c1, 0
88 mrc p15, 0, r2, c2, c0, 0
205 mrc p15, 0, r4, c15, c1, 0
207 mcr p15, 0, r4, c15, c1, 0
211 mrc p15, 0, r2, c2, c0, 0
217 mcr p15, 0, r4, c15, c1, 0
219 mrc p15, 0, r2, c2, c0, 0
312 mrc p15, 0, r1, c15, c1, 0
325 mcr p15, 0, r1, c15, c1, 0
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dpsci_smp.S14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
17 mcr p15, 0, r1, c1, c0, 0
26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
/openbmc/u-boot/arch/arm/lib/
H A Drelocate.S45 mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
54 mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
125 mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
126 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
/openbmc/qemu/tests/tcg/arm/system/
H A Dboot.S47 mcr p15, 0, r0, c12, c0, 0 /* Set up VBAR */
148 mcr p15, 0, r0, c3, c0, 0
157 mcr p15, 0, r0, c1, c0, 2
168 mcr p15, 0, r0, c2, c0, 0
184 mcr p15, 0, r0, c1, c0, 0

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