1*0fdebc5eSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 26509dc74SThomas Petazzoni/* 36509dc74SThomas Petazzoni * Copyright (C) 2014 Marvell 46509dc74SThomas Petazzoni * 56509dc74SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 66509dc74SThomas Petazzoni * Gregory Clement <gregory.clement@free-electrons.com> 76509dc74SThomas Petazzoni */ 86509dc74SThomas Petazzoni 96509dc74SThomas Petazzoni#include <linux/linkage.h> 106509dc74SThomas Petazzoni#include <asm/assembler.h> 116509dc74SThomas Petazzoni 12f746ac32SGregory CLEMENT 13f746ac32SGregory CLEMENTENTRY(armada_38x_scu_power_up) 14f746ac32SGregory CLEMENT mrc p15, 4, r1, c15, c0 @ get SCU base address 15f746ac32SGregory CLEMENT orr r1, r1, #0x8 @ SCU CPU Power Status Register 16969ad77cSStefan Agner mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID 17f746ac32SGregory CLEMENT and r0, r0, #15 18f746ac32SGregory CLEMENT add r1, r1, r0 19f746ac32SGregory CLEMENT mov r0, #0x0 20f746ac32SGregory CLEMENT strb r0, [r1] @ switch SCU power state to Normal mode 21f746ac32SGregory CLEMENT ret lr 22f746ac32SGregory CLEMENTENDPROC(armada_38x_scu_power_up) 23f746ac32SGregory CLEMENT 246509dc74SThomas Petazzoni/* 256509dc74SThomas Petazzoni * This is the entry point through which CPUs exiting cpuidle deep 266509dc74SThomas Petazzoni * idle state are going. 276509dc74SThomas Petazzoni */ 286509dc74SThomas PetazzoniENTRY(armada_370_xp_cpu_resume) 296509dc74SThomas PetazzoniARM_BE8(setend be ) @ go BE8 if entered LE 3077ea46d1SThomas Petazzoni /* 3177ea46d1SThomas Petazzoni * Disable the MMU that might have been enabled in BootROM if 3277ea46d1SThomas Petazzoni * this code is used in the resume path of a suspend/resume 3377ea46d1SThomas Petazzoni * cycle. 3477ea46d1SThomas Petazzoni */ 3577ea46d1SThomas Petazzoni mrc p15, 0, r1, c1, c0, 0 3677ea46d1SThomas Petazzoni bic r1, #1 3777ea46d1SThomas Petazzoni mcr p15, 0, r1, c1, c0, 0 386509dc74SThomas Petazzoni bl ll_add_cpu_to_smp_group 396509dc74SThomas Petazzoni bl ll_enable_coherency 406509dc74SThomas Petazzoni b cpu_resume 416509dc74SThomas PetazzoniENDPROC(armada_370_xp_cpu_resume) 426509dc74SThomas Petazzoni 43e53b1fd4SGregory CLEMENTENTRY(armada_38x_cpu_resume) 44e53b1fd4SGregory CLEMENT /* do we need it for Armada 38x*/ 45e53b1fd4SGregory CLEMENTARM_BE8(setend be ) @ go BE8 if entered LE 46e53b1fd4SGregory CLEMENT bl v7_invalidate_l1 47f746ac32SGregory CLEMENT bl armada_38x_scu_power_up 48e53b1fd4SGregory CLEMENT b cpu_resume 49e53b1fd4SGregory CLEMENTENDPROC(armada_38x_cpu_resume) 50e53b1fd4SGregory CLEMENT 513076cc58SGregory CLEMENT.global mvebu_boot_wa_start 523076cc58SGregory CLEMENT.global mvebu_boot_wa_end 533076cc58SGregory CLEMENT 543076cc58SGregory CLEMENT/* The following code will be executed from SRAM */ 553076cc58SGregory CLEMENTENTRY(mvebu_boot_wa_start) 563076cc58SGregory CLEMENTARM_BE8(setend be) 573076cc58SGregory CLEMENT adr r0, 1f 583076cc58SGregory CLEMENT ldr r0, [r0] @ load the address of the 593076cc58SGregory CLEMENT @ resume register 603076cc58SGregory CLEMENT ldr r0, [r0] @ load the value in the 613076cc58SGregory CLEMENT @ resume register 623076cc58SGregory CLEMENTARM_BE8(rev r0, r0) @ the value is stored LE 633076cc58SGregory CLEMENT mov pc, r0 @ jump to this value 643076cc58SGregory CLEMENT/* 653076cc58SGregory CLEMENT * the last word of this piece of code will be filled by the physical 663076cc58SGregory CLEMENT * address of the boot address register just after being copied in SRAM 673076cc58SGregory CLEMENT */ 683076cc58SGregory CLEMENT1: 693076cc58SGregory CLEMENT .long . 703076cc58SGregory CLEMENTmvebu_boot_wa_end: 713076cc58SGregory CLEMENTENDPROC(mvebu_boot_wa_end) 72