| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | mpc8569_serdes.c | 47 int lane; in fsl_serdes_init() local
59 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
60 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| H A D | cmd_errata.c | 87 unsigned int lane; in check_erratum_a4580() local
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in check_erratum_a4580()
90 if (serdes_lane_enabled(lane)) { in check_erratum_a4580()
92 &srds_regs->lane[serdes_get_lane_idx(lane)]; in check_erratum_a4580()
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| H A D | mpc8536_serdes.c | 96 int lane; in fsl_serdes_init() local
230 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
231 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane]; in fsl_serdes_init()
243 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
244 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane]; in fsl_serdes_init()
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| H A D | mpc8572_serdes.c | 42 int lane; in fsl_serdes_init() local
54 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
55 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| H A D | p1021_serdes.c | 57 int lane; in fsl_serdes_init() local
70 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
71 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| H A D | bsc9132_serdes.c | 82 int lane; in fsl_serdes_init() local
94 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
95 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| /openbmc/linux/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
283 void __iomem *sig_detect_reg, int lane) in netcp_xgbe_serdes_reset_cdr() argument
289 serdes_regs, lane + 1, 5); in netcp_xgbe_serdes_reset_cdr()
298 tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + in netcp_xgbe_serdes_reset_cdr()
430 int lane, int cm, int c1, int c2) in netcp_xgbe_serdes_setup_cm_c1_c2() argument
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | video-interfaces.yaml | 164 # Assume up to 9 physical lane indices
167 An array of physical data lane indexes. Position of an entry determines
169 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
170 assuming the clock lane is on hardware lane 0. If the hardware does not
173 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
177 # Assume up to 9 physical lane indices
180 Physical clock lane index. Position of an entry determines the logical
181 lane number, while the value of an entry indicates physical lane, e.g. for
183 clock lane on hardware lane 0. This property is valid for serial busses
198 lane-polarities:
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | fsl_lsch2_serdes.c | 104 int lane; in serdes_init() local
118 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
119 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); in serdes_init()
180 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
182 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
190 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
192 out_be32(&serdes2_base->lane[i].gcr0, reg); in setup_serdes_volt()
361 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
363 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
371 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | fsl_ls1_serdes.c | 80 int lane; in serdes_init() local
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
90 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); in serdes_init()
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| /openbmc/linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra-xusb.c | 306 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
309 if (lane->funcs[i] == function) in tegra_xusb_padctl_pinmux_set()
312 if (i >= lane->num_funcs) in tegra_xusb_padctl_pinmux_set()
316 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
317 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
340 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_get()
345 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_get()
350 if (value & BIT(lane->iddq)) in tegra_xusb_padctl_pinconf_group_get()
388 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_set()
394 regval &= ~BIT(lane->iddq); in tegra_xusb_padctl_pinconf_group_set()
[all …]
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| /openbmc/linux/drivers/ata/ |
| H A D | sata_highbank.c | 259 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_disable_overrides() local
265 combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); in highbank_cphy_disable_overrides()
270 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_tx_attenuation() local
278 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
281 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
284 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
289 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_rx_mode() local
293 combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_rx_mode()
296 combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_rx_mode()
313 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_override_lane() local
[all …]
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| /openbmc/linux/drivers/nvdimm/ |
| H A D | btt.c | 392 arena->freelist[lane].sub = 1 - arena->freelist[lane].sub; in btt_flog_write()
393 if (++(arena->freelist[lane].seq) == 4) in btt_flog_write()
394 arena->freelist[lane].seq = 1; in btt_flog_write()
396 arena->freelist[lane].has_err = 1; in btt_flog_write()
509 if (arena->freelist[lane].has_err) { in arena_clear_freelist_error()
527 arena->freelist[lane].has_err = 0; in arena_clear_freelist_error()
1202 u32 lane = 0, premap, postmap; in btt_read_pg() local
1276 arena->rtt[lane] = RTT_INVALID; in btt_read_pg()
1287 arena->rtt[lane] = RTT_INVALID; in btt_read_pg()
1336 arena->freelist[lane].has_err = 1; in btt_write_pg()
[all …]
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| /openbmc/u-boot/board/freescale/p2041rdb/ |
| H A D | README | 90 The CPLD is used to control the power sequence and some serdes lane
95 cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
96 lane 6: 0 -> slot1 (Default)
98 lane a: 0 -> slot2 (Default)
100 lane c: 0 -> slot2 (Default)
102 lane d: 0 -> slot2 (Default)
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| /openbmc/u-boot/drivers/phy/marvell/ |
| H A D | comphy_a3700.h | 26 #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (1 - lane) * 0x28) argument
40 #define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (1 - lane) * 0x28) argument
63 static inline void __iomem *sgmiiphy_addr(u32 lane, u32 addr) in sgmiiphy_addr() argument
66 if (lane == 1) in sgmiiphy_addr()
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| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | eth_t102xqds.c | 255 int i, idx, lane, slot, interface; in board_eth_init() local
368 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
371 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
374 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
378 if (lane < 0) in board_eth_init()
381 slot = lane_to_slot[lane]; in board_eth_init()
426 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
428 if (lane < 0) in board_eth_init()
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| /openbmc/linux/drivers/phy/xilinx/ |
| H A D | phy-zynqmp.c | 197 u8 lane; member
278 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
287 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
296 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
334 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
352 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
394 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
449 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
576 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->lane])) in xpsgtr_phy_init()
628 clk_disable_unprepare(gtr_dev->clk[gtr_phy->lane]); in xpsgtr_phy_exit()
[all …]
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| /openbmc/linux/drivers/thunderbolt/ |
| H A D | lc.c | 97 u32 ctrl, lane; in tb_lc_set_port_configured() local
113 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
115 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
118 ctrl |= lane; in tb_lc_set_port_configured()
122 ctrl &= ~lane; in tb_lc_set_port_configured()
155 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
171 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
173 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
176 ctrl |= lane; in tb_lc_set_xdomain_configured()
178 ctrl &= ~lane; in tb_lc_set_xdomain_configured()
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 705 int lane; in mctl_channel_init() local
706 for (lane = 0; lane < 4; ++lane) { in mctl_channel_init()
707 clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff); in mctl_channel_init()
708 clrbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
713 int lane; in mctl_channel_init() local
714 for (lane = 0; lane < 4; ++lane) { in mctl_channel_init()
715 clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff, in mctl_channel_init()
718 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
721 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| H A D | link_dp_cts.c | 230 unsigned int lane; in dp_test_send_phy_test_pattern() local
377 for (lane = 0; lane < in dp_test_send_phy_test_pattern()
379 lane++) { in dp_test_send_phy_test_pattern()
381 dp_get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane); in dp_test_send_phy_test_pattern()
384 link_training_settings.hw_lane_settings[lane].VOLTAGE_SWING = in dp_test_send_phy_test_pattern()
387 link_training_settings.hw_lane_settings[lane].PRE_EMPHASIS = in dp_test_send_phy_test_pattern()
390 link_training_settings.hw_lane_settings[lane].POST_CURSOR2 = in dp_test_send_phy_test_pattern()
392 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03); in dp_test_send_phy_test_pattern()
666 unsigned int lane; in dp_set_test_pattern() local
832 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) in dp_set_test_pattern()
[all …]
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| /openbmc/linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | hdmi_phy.c | 37 u8 lane, pol; in hdmi_phy_parse_lanes() local
59 lane = dx / 2; in hdmi_phy_parse_lanes()
61 phy->lane_function[lane] = i / 2; in hdmi_phy_parse_lanes()
62 phy->lane_polarity[lane] = pol; in hdmi_phy_parse_lanes()
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| /openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | hdmi_phy.c | 46 u8 lane, pol; in hdmi_phy_parse_lanes() local
68 lane = dx / 2; in hdmi_phy_parse_lanes()
70 phy->lane_function[lane] = i / 2; in hdmi_phy_parse_lanes()
71 phy->lane_polarity[lane] = pol; in hdmi_phy_parse_lanes()
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| /openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | parade,ps8622.yaml | 21 lane-count:
70 lane-count:
74 lane-count:
91 lane-count = <2>;
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| /openbmc/u-boot/board/freescale/ls1046aqds/ |
| H A D | eth.c | 270 int i, idx, lane, slot, interface; in board_eth_init() local
369 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
376 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
378 lane_to_slot[lane] = 2; in board_eth_init()
382 lane = 5; in board_eth_init()
384 if (lane < 0) in board_eth_init()
387 slot = lane_to_slot[lane]; in board_eth_init()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_8b_10b.c | 363 uint8_t lane = 0; in dp_perform_8b_10b_link_training() local
399 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_perform_8b_10b_link_training()
400 lt_settings->dpcd_lane_settings[lane].raw = 0; in dp_perform_8b_10b_link_training()
401 lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0; in dp_perform_8b_10b_link_training()
402 lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0; in dp_perform_8b_10b_link_training()
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