Lines Matching refs:lane
216 u8 lane; member
299 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
308 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
317 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
381 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
395 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
399 if (gtr_phy->refclk == gtr_phy->lane) in xpsgtr_configure_pll()
400 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
403 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
442 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
490 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
497 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
498 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
1019 gtr_phy->lane = port; in xpsgtr_probe()