| /openbmc/openbmc/poky/meta/conf/machine/include/arm/ |
| H A D | arch-arm64.inc | 5 TUNEVALID[aarch64] = "Enable instructions for aarch64"
41 # Emit branch protection (PAC/BTI) instructions. On hardware that doesn't
42 # support these they're meaningless NOP instructions, so there's very little
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| /openbmc/linux/arch/mips/crypto/ |
| H A D | Kconfig | 31 Architecture: mips OCTEON using crypto instructions, when available
51 Architecture: mips OCTEON using crypto instructions, when available
61 Architecture: mips OCTEON using crypto instructions, when available
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | pointer-authentication.rst | 25 The extension adds instructions to insert a valid PAC into a pointer,
30 A subset of these instructions have been allocated from the HINT
32 these instructions behave as NOPs. Applications and libraries using
33 these instructions operate correctly regardless of the presence of the
57 with HINT space pointer authentication instructions protecting
107 register. Any attempt to use the Pointer Authentication instructions will
128 instructions to sign and authenticate function pointers and other pointers
135 but before executing any PAC instructions.
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| /openbmc/linux/Documentation/virt/ |
| H A D | paravirt_ops.rst | 16 corresponding to low-level critical instructions and high-level
28 Usually these operations correspond to low-level critical instructions. They
34 because they include sensitive instructions or some code paths in
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| /openbmc/linux/tools/perf/Documentation/ |
| H A D | intel-hybrid.txt | 29 [Fixed Counter: Counts the number of instructions retired. Unit: cpu_atom]
31 [Number of instructions retired. Fixed Counter - architectural event. Unit: cpu_core]
184 cpu_core/instructions/,
185 cpu_atom/instructions/,
199 perf stat -e cpu_core/cycles/,cpu_atom/instructions/
200 perf stat -e '{cpu_core/cycles/,cpu_core/instructions/}'
202 But '{cpu_core/cycles/,cpu_atom/instructions/}' will return
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| /openbmc/qemu/docs/system/openrisc/ |
| H A D | emulation.rst | 13 for most Class II (optional) instructions.
15 For information on all OpenRISC instructions please refer to the latest
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| /openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/tremor/tremor/ |
| H A D | tremor-arm-thumb2.patch | 3 Subject: [PATCH] tremor: add IT instructions for arm thumb2 tune flags.
7 In Thumb-2, most instructions do not have a built in condition code (except for
8 conditional branches). Instead, short sequences of instructions which are to be
10 describes the condition and which of the following instructions should be
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| /openbmc/linux/tools/perf/tests/shell/ |
| H A D | stat.sh | 111 if perf stat --cputype="123" -e instructions true > /dev/null 2>&1
140 if ! perf stat --cputype="$pmu" -e instructions true 2>&1 | grep -E -q "instructions"
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | phys2virt.S | 41 mov r0, r3, lsr #21 @ constant for add/sub instructions
77 @ In the non-LPAE case, all patchable instructions are MOVW
78 @ instructions, where we need to patch in the offset into the
131 @ in BE8, we load data in BE, but instructions still in LE
155 @ In the non-LPAE case, all patchable instructions are ADD or SUB
156 @ instructions, where we need to patch in the offset into the
173 @ instructions based on bits 23:22 of the opcode, and ADD/SUB can be
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| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | README | 74 Build instructions:
87 on EVM. See instructions at below link for installing CCS on a Windows PC.
91 on EVM. Follow instructions at
98 and Power ON the EVM. Follow instructions to connect serial port of EVM to
104 The instructions provided in the above link uses a script for
132 SPI NOR Flash programming instructions
135 instructions:
153 AEMIF NAND Flash programming instructions
156 instructions:
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| /openbmc/linux/drivers/media/pci/tw68/ |
| H A D | tw68-risc.c | 137 u32 instructions, fields; in tw68_risc_buffer() local
151 instructions = fields * (1 + (((bpl + padding) * lines) / in tw68_risc_buffer()
153 buf->size = instructions * 8; in tw68_risc_buffer()
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| /openbmc/qemu/target/ppc/translate/ |
| H A D | processor-ctrl-impl.c.inc | 2 * Power ISA decode for Storage Control instructions
28 * Before Power ISA 2.07, processor control instructions were only
52 * Before Power ISA 2.07, processor control instructions were only
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| /openbmc/linux/arch/nios2/platform/ |
| H A D | Kconfig.platform | 53 comment "Nios II instructions"
82 bool "Enable BMX instructions"
86 the BMX Bit Manipulation Extension instructions. Enables
90 bool "Enable CDX instructions"
94 the CDX Bit Manipulation Extension instructions. Enables
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| /openbmc/linux/Documentation/powerpc/ |
| H A D | elf_hwcaps.rst | 48 The Power ISA uses the term "facility" to describe a class of instructions,
52 instructions that can be used differ between the v3.0B and v3.1B ISA
59 classes of instructions and operating modes which may be optional or
96 The processor has a unified L1 cache for instructions and data, as
138 instructions with the sequence (as described in, e.g., POWER9 Processor
201 v2.07 crypto instructions are available.
213 quad-precision instructions and data types.
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| /openbmc/linux/arch/m68k/ifpsp060/ |
| H A D | fplsp.doc | 36 FP instructions not implemented in 68060 hardware. These
37 instructions normally take exception vector #11
40 By re-compiling a program that uses these instructions, and
42 instructions, a program can avoid the overhead associated
110 this exception using implemented floating-point instructions.
120 The package does not attempt to correctly emulate instructions
126 subroutine calls for all fp instructions. The code does NOT emulate
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| /openbmc/u-boot/doc/imx/mkimage/ |
| H A D | mxsimage.txt | 39 subsequent instructions or code. Exactly one section must be selected
40 as bootable, usually the one containing the instructions and data to
49 - After a "TAG" instruction, any of the following instructions may follow
106 - The DCD block must be followed by one of the following instructions. All
107 of the instructions operate either on 1, 2 or 4 bytes. This is selected by
149 Here is a mapping between the above instructions and the BootROM output:
169 instructions contained in the SB image. It will also check if the various
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| /openbmc/qemu/tests/tcg/i386/ |
| H A D | README | 6 This program executes most of the 16 bit and 32 bit x86 instructions and
21 This program executes most SSE/AVX instructions and generates a text output,
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| /openbmc/linux/arch/openrisc/ |
| H A D | Kconfig | 125 This config enables gcc to generate l.cmov instructions when compiling
138 This config enables gcc to generate l.ror instructions when compiling
151 This config enables gcc to generate l.rori instructions when compiling
161 bool "Have instructions l.ext* for sign extension"
164 This config enables gcc to generate l.ext* instructions when compiling
169 l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
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| /openbmc/linux/Documentation/arch/arm/nwfpe/ |
| H A D | netwinder-fpe.rst | 9 instructions. It follows the conventions in the ARM manual.
28 These instructions are fully implemented.
40 These instructions are fully implemented. They store/load three words
49 Conversions, read/write status/control register instructions
62 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
66 Compare instructions
95 equivalent to the MUF/DVF/RDV instructions. This is acceptable according
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| /openbmc/linux/Documentation/admin-guide/hw-vuln/ |
| H A D | special-register-buffer-data-sampling.rst | 13 When RDRAND, RDSEED and EGETKEY instructions are used, the data is moved
65 EGETKEY instructions to overwrite secret special register data in the shared
69 During execution of the RDRAND, RDSEED, or EGETKEY instructions, off-core
76 #. RDRAND, RDSEED, or EGETKEY instructions have higher latency.
87 the mitigation for RDRAND and RDSEED instructions executed outside of Intel
|
| /openbmc/linux/drivers/acpi/apei/ |
| H A D | apei-internal.h | 32 u32 instructions; member
39 u32 instructions,
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| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_privileged.c.inc | 2 * RISC-V translation routines for the RISC-V privileged instructions.
48 * Uncompressed instructions are required so that the sequence is easy
51 * The three instructions are required to lie in the same page so
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| /openbmc/qemu/docs/devel/ |
| H A D | tcg-plugins.rst | 37 ops to count and break down the hint instructions by type.
93 instructions in a block of instructions and optionally register
94 callbacks to some or all instructions when they are executed.
112 details of instructions and system configuration only through the
184 number of instructions executed on each core/thread::
213 Only instrument instructions matching the string prefix. Will show
214 some basic stats including how many instructions have executed since
291 count, number of instructions and execution count. This will work best
344 types of instructions. It has a number of options to refine which get
493 the output can be filtered to only track certain instructions or
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| H A D | multi-thread-tcg.rst | 209 coherent state when it next runs its work (in a few instructions
287 Aside from explicit standalone memory barrier instructions there are
291 special variants of load/store instructions that imply acquire/release
321 This includes a class of instructions for controlling system cache
322 behaviour. While QEMU doesn't model cache behaviour these instructions
330 modern ISAs: atomic instructions and exclusive regions.
337 The second type offer a pair of load/store instructions which offer a
339 load and store instructions. An example of this is Arm's ldrex/strex
351 - Support classic atomic instructions
360 can be used directly or combined to emulate other instructions like
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| /openbmc/linux/Documentation/devicetree/bindings/riscv/ |
| H A D | extensions.yaml | 86 The standard A extension for atomic instructions, as ratified in the
109 The standard C extension for compressed instructions, as ratified in
171 acceleration instructions as ratified at commit 6d33919 ("Merge pull
190 instructions as ratified at commit 6d33919 ("Merge pull request #158
200 The standard Zicbop extension for cache-block prefetch instructions
218 instructions, as ratified in the 20191213 version of the
|