Lines Matching refs:instructions
209 coherent state when it next runs its work (in a few instructions
287 Aside from explicit standalone memory barrier instructions there are
291 special variants of load/store instructions that imply acquire/release
321 This includes a class of instructions for controlling system cache
322 behaviour. While QEMU doesn't model cache behaviour these instructions
330 modern ISAs: atomic instructions and exclusive regions.
337 The second type offer a pair of load/store instructions which offer a
339 load and store instructions. An example of this is Arm's ldrex/strex
351 - Support classic atomic instructions
360 can be used directly or combined to emulate other instructions like
361 Arm's ldrex/strex instructions. While they are susceptible to the ABA