| /openbmc/qemu/docs/system/arm/ |
| H A D | sabrelite.rst | 13 * Up to 4 Cortex-A9 cores
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| H A D | xlnx-versal-virt.rst | 18 limitations. Currently, we support the following cores and devices:
20 Implemented CPU cores:
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | pmu.yaml | 14 ARM cores often have a PMU for counting cpu and cache events like cache misses
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | arm,arch_timer.yaml | 13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | nxp,imx-mipi-csi2.yaml | 21 own. This binding thus covers both IP cores.
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | xlnx,zynqmp-r5fss.yaml | 28 lock-step mode(Both RPU cores execute the same code in lock-step,
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8dxl.dtsi | 37 /* We have 1 clusters with 2 Cortex-A35 cores */
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| /openbmc/linux/drivers/gpu/drm/v3d/ |
| H A D | v3d_drv.h | 95 u32 cores; member
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| /openbmc/linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_vcap_impl.c | 1991 int idx, cores; in sparx5_vcap_block_alloc() local
2016 cores = spx5_rd(sparx5, VCAP_ES0_CORE_CNT); in sparx5_vcap_block_alloc()
2017 for (idx = 0; idx < cores; ++idx) { in sparx5_vcap_block_alloc()
2028 cores = spx5_rd(sparx5, VCAP_ES2_CORE_CNT); in sparx5_vcap_block_alloc()
2029 for (idx = 0; idx < cores; ++idx) { in sparx5_vcap_block_alloc()
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| /openbmc/linux/Documentation/staging/ |
| H A D | rpmsg.rst | 21 and each of the other three cores (two M3 cores and a DSP) is running
44 OMAP4, remote cores and hardware accelerators may have direct access to the
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| /openbmc/qemu/qapi/ |
| H A D | machine.json | 991 # For pseries machine type started with -smp 2,cores=2,maxcpus=4 -cpu
1606 # @drawers, @books, @sockets, @dies, @clusters, @cores, @threads.
1612 # is the parent container of cores.
1629 # @cores: number of cores per parent container
1642 '*cores': 'int',
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| /openbmc/u-boot/board/freescale/mpc8572ds/ |
| H A D | README | 136 5. Bring up two cores separately:
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| /openbmc/qemu/docs/system/ |
| H A D | gdb.rst | 94 U54 cores. Here the E51 is the only thread in the first inferior, and
95 the U54 cores are all threads in the second inferior.
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| /openbmc/linux/drivers/soc/qcom/ |
| H A D | Kconfig | 123 cores on some Qualcomm SoCs.
242 to manage cores, L2 low power modes and to configure the internal
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| /openbmc/linux/Documentation/bpf/ |
| H A D | cpumasks.rst | 14 a task is affinitized to, but they can also be used to e.g. track which cores
15 are associated with a scheduling domain, which cores on a machine are idle,
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| /openbmc/qemu/docs/devel/ |
| H A D | multi-thread-tcg.rst | 20 being emulated gained additional cores and per-core performance gains
81 translation buffer which contains code running on all cores. Any
334 other cores sharing access to the memory. The classic example is the
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | marvell.rst | 471 The XScale cores were designed by Intel, and shipped by Marvell in the older
473 and that evolved into Sheeva. The XScale and Feroceon cores were phased out
474 over time and replaced with Sheeva cores in later products, which subsequently
475 got replaced with licensed ARM Cortex-A cores.
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| /openbmc/linux/drivers/accel/habanalabs/common/ |
| H A D | command_submission.c | 2452 u32 *cores; in cs_ioctl_engine_cores() local
2469 cores = kmalloc_array(num_engine_cores, sizeof(u32), GFP_KERNEL); in cs_ioctl_engine_cores()
2470 if (!cores) in cs_ioctl_engine_cores()
2473 if (copy_from_user(cores, engine_cores_arr, num_engine_cores * sizeof(u32))) { in cs_ioctl_engine_cores()
2475 kfree(cores); in cs_ioctl_engine_cores()
2479 rc = hdev->asic_funcs->set_engine_cores(hdev, cores, num_engine_cores, core_command); in cs_ioctl_engine_cores()
2480 kfree(cores); in cs_ioctl_engine_cores()
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| /openbmc/linux/arch/mips/ |
| H A D | Kconfig | 1289 cores implements the MIPS64R2 instruction set with many extensions,
1299 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1321 bool "Emulate the CPUCFG instruction on older Loongson cores"
1328 cores, back to Loongson-3A1000.
1525 level features like up to six P5600 calculation cores, CM2 with L2
1643 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
2093 only on cnMIPS cores. Note that you will need a suitable Linux
2208 on cores with the MT ASE and uses the available VPEs to implement
2222 when dealing with MIPS MT enabled cores at a cost of slightly
2303 Select this if you wish to run an SMP kernel across multiple cores
[all …]
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | coretemp.rst | 33 show the temperature of all cores inside a package under a single device
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| /openbmc/linux/drivers/gpu/drm/msm/ |
| H A D | NOTES | 15 + zero, one, or two 2d cores (z180)
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| /openbmc/u-boot/doc/ |
| H A D | README.mpc85xx | 4 Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
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| /openbmc/linux/drivers/thermal/intel/ |
| H A D | Kconfig | 54 addition to DTSs on CPU cores. Each DTS will be registered as a
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| /openbmc/linux/drivers/media/platform/amphion/ |
| H A D | vpu.h | 65 struct list_head cores; member
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| /openbmc/linux/drivers/net/wireless/intel/iwlwifi/ |
| H A D | iwl-config.h | 473 u8 cores; member
|