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Searched refs:clk (Results 51 – 75 of 4353) sorted by relevance

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/openbmc/linux/drivers/clk/ux500/
H A Dclk-prcmu.c210 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in clk_reg_prcmu()
211 if (!clk) in clk_reg_prcmu()
231 return &clk->hw; in clk_reg_prcmu()
234 kfree(clk); in clk_reg_prcmu()
302 return prcmu_config_clkout(clk->clkout_id, clk->source, clk->divider); in clk_prcmu_clkout_prepare()
311 ret = prcmu_config_clkout(clk->clkout_id, clk->source, 0); in clk_prcmu_clkout_unprepare()
329 return clk->source; in clk_prcmu_clkout_get_parent()
377 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in clk_reg_prcmu_clkout()
378 if (!clk) in clk_reg_prcmu_clkout()
396 return &clk->hw; in clk_reg_prcmu_clkout()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgf100.c188 return read_clk(clk, 0x00); in gf100_clk_read()
190 return read_clk(clk, 0x01); in gf100_clk_read()
192 return read_clk(clk, 0x02); in gf100_clk_read()
194 return read_clk(clk, 0x07); in gf100_clk_read()
196 return read_clk(clk, 0x08); in gf100_clk_read()
432 if (!clk->eng[j].freq) in gf100_clk_prog()
434 stage[i].exec(clk, j); in gf100_clk_prog()
445 memset(clk->eng, 0x00, sizeof(clk->eng)); in gf100_clk_tidy()
474 struct gf100_clk *clk; in gf100_clk_new() local
476 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in gf100_clk_new()
[all …]
H A Dgk20a.c136 clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl)); in gk20a_pllg_calc_mnp()
144 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { in gk20a_pllg_calc_mnp()
314 gk20a_pllg_disable(clk); in gk20a_pllg_program_mnp()
494 ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll); in gk20a_clk_prog()
496 ret = gk20a_pllg_program_mnp(clk, &clk->pll); in gk20a_clk_prog()
627 clk->params = params; in gk20a_clk_ctor()
628 clk->parent_rate = clk_get_rate(tdev->clk); in gk20a_clk_ctor()
644 struct gk20a_clk *clk; in gk20a_clk_new() local
647 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in gk20a_clk_new()
648 if (!clk) in gk20a_clk_new()
[all …]
H A Dgk104.c201 return read_mem(clk); in gk104_clk_read()
203 return read_clk(clk, 0x00); in gk104_clk_read()
205 return read_clk(clk, 0x01); in gk104_clk_read()
207 return read_clk(clk, 0x02); in gk104_clk_read()
209 return read_clk(clk, 0x07); in gk104_clk_read()
469 if (!clk->eng[j].freq) in gk104_clk_prog()
471 stage[i].exec(clk, j); in gk104_clk_prog()
482 memset(clk->eng, 0x00, sizeof(clk->eng)); in gk104_clk_tidy()
510 struct gk104_clk *clk; in gk104_clk_new() local
512 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in gk104_clk_new()
[all …]
H A Dnv50.c32 read_div(struct nv50_clk *clk) in read_div() argument
154 return read_pll_src(clk, base); in read_pll_ref()
164 u32 ref = read_pll_ref(clk, base); in read_pll()
194 struct nv50_clk *clk = nv50_clk(base); in nv50_clk_read() local
337 pll.refclk = read_pll_ref(clk, reg); in calc_pll()
404 out = read_pll(clk, 0x004030); in nv50_clk_calc()
499 return clk_exec(&clk->hwsq, true); in nv50_clk_prog()
506 clk_exec(&clk->hwsq, false); in nv50_clk_tidy()
513 struct nv50_clk *clk; in nv50_clk_new_() local
516 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in nv50_clk_new_()
[all …]
H A Dnv40.c82 read_clk(struct nv40_clk *clk, u32 src) in read_clk() argument
86 return read_pll_2(clk, 0x004000); in read_clk()
88 return read_pll_1(clk, 0x004008); in read_clk()
114 return read_pll_2(clk, 0x4020); in nv40_clk_read()
162 clk->npll_coef = (N1 << 8) | M1; in nv40_clk_calc()
176 clk->ctrl = 0x00000223; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
179 clk->ctrl = 0x00000333; in nv40_clk_calc()
224 struct nv40_clk *clk; in nv40_clk_new() local
226 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in nv40_clk_new()
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c187 struct exynos4_clock *clk = in exynos4_get_pll_clk() local
247 struct exynos5_clock *clk = in exynos5_get_pll_clk() local
369 struct exynos5_clock *clk = in exynos5_get_periph_rate() local
1473 reg = &clk->div_peric1; in exynos5_set_spi_clk()
1478 reg = &clk->div_peric1; in exynos5_set_spi_clk()
1483 reg = &clk->div_peric2; in exynos5_set_spi_clk()
1531 reg = &clk->div_peric1; in exynos5420_set_spi_clk()
1537 reg = &clk->div_peric1; in exynos5420_set_spi_clk()
1543 reg = &clk->div_peric1; in exynos5420_set_spi_clk()
1549 reg = &clk->div_isp1; in exynos5420_set_spi_clk()
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-lpcg-scu.c56 if (clk->hw_gate) in clk_lpcg_scu_enable()
60 writel(reg, clk->reg); in clk_lpcg_scu_enable()
96 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in __imx_clk_lpcg_scu()
97 if (!clk) in __imx_clk_lpcg_scu()
100 clk->reg = reg; in __imx_clk_lpcg_scu()
112 hw = &clk->hw; in __imx_clk_lpcg_scu()
115 kfree(clk); in __imx_clk_lpcg_scu()
131 kfree(clk); in imx_clk_lpcg_scu_unregister()
138 clk->state = readl_relaxed(clk->reg); in imx_clk_lpcg_scu_suspend()
153 writel(clk->state, clk->reg); in imx_clk_lpcg_scu_resume()
[all …]
/openbmc/linux/sound/soc/qcom/qdsp6/
H A Dq6dsp-lpass-clocks.c42 return cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes, in clk_q6dsp_prepare()
51 cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes, in clk_q6dsp_unprepare()
60 clk->rate = rate; in clk_q6dsp_set_rate()
70 return clk->rate; in clk_q6dsp_recalc_rate()
92 return cc->desc->lpass_vote_clk(clk->dev, clk->q6dsp_clk_id, in clk_vote_q6dsp_block()
93 clk_hw_get_name(&clk->hw), &clk->handle); in clk_vote_q6dsp_block()
101 cc->desc->lpass_unvote_clk(clk->dev, clk->q6dsp_clk_id, clk->handle); in clk_unvote_q6dsp_block()
157 clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); in q6dsp_clock_dev_probe()
158 if (!clk) in q6dsp_clock_dev_probe()
161 clk->dev = dev; in q6dsp_clock_dev_probe()
[all …]
/openbmc/linux/drivers/clk/ti/
H A Ddpll3xxx.c52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
323 __clk_get_name(clk->hw.clk), ref_rate / 70); in omap3_noncore_dpll_ssc_program()
362 __clk_get_name(clk->hw.clk)); in omap3_noncore_dpll_ssc_program()
534 r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap3_noncore_dpll_enable()
569 if (clk->clkdm) in omap3_noncore_dpll_disable()
570 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in omap3_noncore_dpll_disable()
733 if (!clk || !clk->dpll_data) in omap3_dpll_autoidle_read()
762 if (!clk || !clk->dpll_data) in omap3_dpll_allow_idle()
792 if (!clk || !clk->dpll_data) in omap3_dpll_deny_idle()
926 _omap3_dpll_write_clken(clk, clk->context); in omap3_core_dpll_restore_context()
[all …]
H A Dclockdomain.c36 struct clk_hw_omap *clk; in omap2_clkops_enable_clkdm() local
39 clk = to_clk_hw_omap(hw); in omap2_clkops_enable_clkdm()
53 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_clkops_enable_clkdm()
71 struct clk_hw_omap *clk; in omap2_clkops_disable_clkdm() local
87 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in omap2_clkops_disable_clkdm()
104 if (!clk->clkdm_name) in omap2_init_clk_clkdm()
113 clk->clkdm = clkdm; in omap2_init_clk_clkdm()
124 struct clk *clk; in of_ti_clockdomain_setup() local
134 if (IS_ERR(clk)) { in of_ti_clockdomain_setup()
143 clk_put(clk); in of_ti_clockdomain_setup()
[all …]
/openbmc/linux/drivers/clk/samsung/
H A DMakefile6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o
8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o
9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o
10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o
12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o
18 obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
20 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
24 obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
25 obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
[all …]
/openbmc/u-boot/arch/arm/include/asm/kona-common/
H A Dclk.h13 struct clk;
17 struct clk *clk_get(const char *id);
18 int clk_enable(struct clk *clk);
19 void clk_disable(struct clk *clk);
20 unsigned long clk_get_rate(struct clk *clk);
21 long clk_round_rate(struct clk *clk, unsigned long rate);
22 int clk_set_rate(struct clk *clk, unsigned long rate);
23 int clk_set_parent(struct clk *clk, struct clk *parent);
24 struct clk *clk_get_parent(struct clk *clk);
/openbmc/linux/drivers/clk/meson/
H A Dclk-phase.c16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data() argument
18 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
50 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_set_phase() local
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
83 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_sync() local
88 val = meson_parm_read(clk->map, &tph->ph0); in meson_clk_triphase_sync()
89 meson_parm_write(clk->map, &tph->ph1, val); in meson_clk_triphase_sync()
90 meson_parm_write(clk->map, &tph->ph2, val); in meson_clk_triphase_sync()
[all …]
/openbmc/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-afe-clk.c97 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), in mt8183_init_clock()
99 if (!afe_priv->clk) in mt8183_init_clock()
104 if (IS_ERR(afe_priv->clk[i])) { in mt8183_init_clock()
107 PTR_ERR(afe_priv->clk[i])); in mt8183_init_clock()
108 return PTR_ERR(afe_priv->clk[i]); in mt8183_init_clock()
135 afe_priv->clk[CLK_CLK26M]); in mt8183_afe_enable_clock()
269 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
279 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
293 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
298 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk_test.c219 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_get_rate() local
240 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_set_get_rate() local
265 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_set_set_get_rate() local
291 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_round_set_get_rate() local
361 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_uncached_get_rate() local
385 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_uncached_set_range() local
414 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_uncached_updated_rate_set_range() local
509 struct clk *clk = clk_hw_get_clk(hw, NULL); in clk_test_multiple_parents_mux_get_parent() local
772 struct clk *clk, *parent; in clk_test_orphan_transparent_multiple_parent_mux_set_parent_put() local
2275 struct clk *clk; member
[all …]
H A Dclk-devres.c8 struct clk *clk; member
9 void (*exit)(struct clk *clk);
24 int (*init)(struct clk *clk), in __devm_clk_get() argument
25 void (*exit)(struct clk *clk)) in __devm_clk_get() argument
28 struct clk *clk; in __devm_clk_get() local
47 state->clk = clk; in __devm_clk_get()
52 return clk; in __devm_clk_get()
56 clk_put(clk); in __devm_clk_get()
195 void devm_clk_put(struct device *dev, struct clk *clk) in devm_clk_put() argument
209 struct clk *clk; in devm_get_clk_from_child() local
[all …]
H A Dclk-sp7021.c178 clk->p[SEL_FRA] = 0; in plltv_integer_div()
179 clk->p[DIVR] = r; in plltv_integer_div()
180 clk->p[DIVN] = n; in plltv_integer_div()
327 writel(r0, clk->reg); in plltv_set_rate()
396 clk->p[0] = i; in plla_round_rate()
430 ret = sp_pll_calc_div(clk, rate) * clk->brate; in sp_pll_round_rate()
473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; in sp_pll_recalc_rate()
498 u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift); in sp_pll_set_rate()
515 writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); in sp_pll_enable()
524 writel(BIT(clk->pd_bit + 16), clk->reg); in sp_pll_disable()
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c73 static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
234 static int meson_clk_enable(struct clk *clk) in meson_clk_enable() argument
236 return meson_set_gate_by_id(clk, clk->id, true); in meson_clk_enable()
239 static int meson_clk_disable(struct clk *clk) in meson_clk_disable() argument
241 return meson_set_gate_by_id(clk, clk->id, false); in meson_clk_disable()
567 static unsigned long meson_clk81_get_rate(struct clk *clk) in meson_clk81_get_rate() argument
797 static ulong meson_clk_get_rate(struct clk *clk) in meson_clk_get_rate() argument
799 return meson_clk_get_rate_by_id(clk, clk->id); in meson_clk_get_rate()
802 static int meson_clk_set_parent(struct clk *clk, struct clk *parent) in meson_clk_set_parent() argument
804 return meson_mux_set_parent(clk, clk->id, parent->id); in meson_clk_set_parent()
[all …]
H A Dclk-hsdk-cgu.c279 ulong (*get_rate)(struct clk *clk);
280 ulong (*set_rate)(struct clk *clk, ulong rate);
281 int (*disable)(struct clk *clk);
437 if (hsdk_pll_is_err(clk)) in hsdk_pll_comm_update_rate()
488 return clk->pll_devdata->update_rate(clk, best_rate, in pll_set()
502 hsdk_idiv_write(clk, 0); in idiv_off()
562 clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft; in axi_clk_set()
600 clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft; in tun_clk_set()
650 clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft; in hsdk_prepare_clock_tree_branch()
651 clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft; in hsdk_prepare_clock_tree_branch()
[all …]
/openbmc/qemu/include/hw/
H A Dclock.h114 void clock_setup_canonical_path(Clock *clk);
150 void clock_clear_callback(Clock *clk);
176 return clk->source != NULL; in clock_has_source()
210 void clock_propagate(Clock *clk);
223 if (clock_set(clk, value)) { in clock_update()
224 clock_propagate(clk); in clock_update()
246 return clk->period; in clock_get()
323 if (clk->period == 0) { in clock_ns_to_ticks()
327 divu128(&lo, &hi, clk->period); in clock_ns_to_ticks()
339 return clock_get(clk) != 0; in clock_is_enabled()
[all …]
/openbmc/linux/drivers/clk/sunxi/
H A DMakefile6 obj-$(CONFIG_CLK_SUNXI) += clk-factors.o
8 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sunxi.o
9 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-codec.o
10 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-hosc.o
11 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-mod1.o
12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
13 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-ve.o
14 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a20-gmac.o
15 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-mod0.o
18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
[all …]
/openbmc/linux/arch/mips/lantiq/xway/
H A Dgptu.c95 static int gptu_enable(struct clk *clk) in gptu_enable() argument
112 static void gptu_disable(struct clk *clk) in gptu_disable() argument
124 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); in clkdev_add_gptu() local
126 if (!clk) in clkdev_add_gptu()
130 clk->cl.clk = clk; in clkdev_add_gptu()
133 clk->bits = timer; in clkdev_add_gptu()
139 struct clk *clk; in gptu_probe() local
153 if (IS_ERR(clk)) { in gptu_probe()
157 clk_enable(clk); in gptu_probe()
166 clk_disable(clk); in gptu_probe()
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7780.c22 static void master_clk_init(struct clk *clk) in master_clk_init() argument
31 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
34 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
41 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
51 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
74 static unsigned long shyway_clk_recalc(struct clk *clk) in shyway_clk_recalc() argument
84 static struct clk sh7780_shyway_clk = {
104 struct clk *clk; in arch_clk_init() local
109 clk = clk_get(NULL, "master_clk"); in arch_clk_init()
113 clkp->parent = clk; in arch_clk_init()
[all …]
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c42 static int mtk_clk_find_parent_rate(struct clk *clk, int id, in mtk_clk_find_parent_rate() argument
184 static ulong mtk_apmixedsys_get_rate(struct clk *clk) in mtk_apmixedsys_get_rate() argument
202 static int mtk_apmixedsys_enable(struct clk *clk) in mtk_apmixedsys_enable() argument
231 static int mtk_apmixedsys_disable(struct clk *clk) in mtk_apmixedsys_disable() argument
307 static ulong mtk_topckgen_get_rate(struct clk *clk) in mtk_topckgen_get_rate() argument
317 return mtk_topckgen_get_mux_rate(clk, clk->id - in mtk_topckgen_get_rate()
321 static int mtk_topckgen_enable(struct clk *clk) in mtk_topckgen_enable() argument
349 static int mtk_topckgen_disable(struct clk *clk) in mtk_topckgen_disable() argument
370 static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent) in mtk_topckgen_set_parent() argument
383 static int mtk_clk_gate_enable(struct clk *clk) in mtk_clk_gate_enable() argument
[all …]

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