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Searched refs:CONFIG_SYS_CLK_FREQ (Results 101 – 125 of 178) sorted by relevance

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/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dspl.c47 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dspl.c55 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
/openbmc/u-boot/include/configs/
H A Dcalimain.h23 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) macro
H A Dls2080a_simu.h11 #define CONFIG_SYS_CLK_FREQ 100000000 macro
H A Dedb93xx.h74 #define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ macro
H A DMPC837XERDB.h35 #ifndef CONFIG_SYS_CLK_FREQ
36 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN macro
H A DMPC837XEMDS.h26 #ifndef CONFIG_SYS_CLK_FREQ
27 #define CONFIG_SYS_CLK_FREQ 66000000 macro
H A Dls1021aqds.h33 #define CONFIG_SYS_CLK_FREQ 100000000 macro
37 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() macro
H A Dipam390.h25 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) macro
H A DMPC8555CDS.h27 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ macro
H A DMPC8541CDS.h27 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ macro
H A Dls1021aiot.h21 #define CONFIG_SYS_CLK_FREQ 100000000 macro
H A DMPC8641HPCN.h60 #ifndef CONFIG_SYS_CLK_FREQ
64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) macro
H A Dda850evm.h33 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) macro
H A Dcontrolcenterd.h50 #define CONFIG_SYS_CLK_FREQ 66666600 macro
H A DMPC8568MDS.h27 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()… macro
H A Dls1046ardb.h11 #define CONFIG_SYS_CLK_FREQ 100000000 macro
H A Domapl138_lcdk.h31 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) macro
/openbmc/u-boot/board/renesas/lager/
H A Dlager.c46 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) in s_init()
/openbmc/u-boot/board/freescale/t104xrdb/
H A Dspl.c27 return CONFIG_SYS_CLK_FREQ; in get_board_sys_clk()
/openbmc/u-boot/drivers/serial/
H A Dserial_lpuart.c99 #ifndef CONFIG_SYS_CLK_FREQ
100 #define CONFIG_SYS_CLK_FREQ 0 macro
105 return CONFIG_SYS_CLK_FREQ; in get_lpuart_clk()
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c69 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dclock.c40 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; in get_sys_info()
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dspl.c27 return CONFIG_SYS_CLK_FREQ; in get_board_sys_clk()
/openbmc/u-boot/arch/arc/lib/
H A Dcpu.c17 gd->cpu_clk = CONFIG_SYS_CLK_FREQ; in arch_cpu_init()

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