1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
218c01445SPrabhakar Kushwaha /* Copyright 2013 Freescale Semiconductor, Inc.
318c01445SPrabhakar Kushwaha */
418c01445SPrabhakar Kushwaha
518c01445SPrabhakar Kushwaha #include <common.h>
624b852a7SSimon Glass #include <console.h>
7203e94f6SSimon Glass #include <environment.h>
818c01445SPrabhakar Kushwaha #include <malloc.h>
918c01445SPrabhakar Kushwaha #include <ns16550.h>
1018c01445SPrabhakar Kushwaha #include <nand.h>
1118c01445SPrabhakar Kushwaha #include <i2c.h>
1218c01445SPrabhakar Kushwaha #include <mmc.h>
1318c01445SPrabhakar Kushwaha #include <fsl_esdhc.h>
1418c01445SPrabhakar Kushwaha #include <spi_flash.h>
1500233528STang Yuantian #include "../common/sleep.h"
16ea022a37SSimon Glass #include "../common/spl.h"
1718c01445SPrabhakar Kushwaha
1818c01445SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR;
1918c01445SPrabhakar Kushwaha
get_effective_memsize(void)2018c01445SPrabhakar Kushwaha phys_size_t get_effective_memsize(void)
2118c01445SPrabhakar Kushwaha {
2218c01445SPrabhakar Kushwaha return CONFIG_SYS_L3_SIZE;
2318c01445SPrabhakar Kushwaha }
2418c01445SPrabhakar Kushwaha
get_board_sys_clk(void)2518c01445SPrabhakar Kushwaha unsigned long get_board_sys_clk(void)
2618c01445SPrabhakar Kushwaha {
2718c01445SPrabhakar Kushwaha return CONFIG_SYS_CLK_FREQ;
2818c01445SPrabhakar Kushwaha }
2918c01445SPrabhakar Kushwaha
get_board_ddr_clk(void)3018c01445SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void)
3118c01445SPrabhakar Kushwaha {
3218c01445SPrabhakar Kushwaha return CONFIG_DDR_CLK_FREQ;
3318c01445SPrabhakar Kushwaha }
3418c01445SPrabhakar Kushwaha
3518c01445SPrabhakar Kushwaha #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
board_init_f(ulong bootflag)3618c01445SPrabhakar Kushwaha void board_init_f(ulong bootflag)
3718c01445SPrabhakar Kushwaha {
3818c01445SPrabhakar Kushwaha u32 plat_ratio, sys_clk, uart_clk;
399f074e67SPrabhakar Kushwaha #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
4018c01445SPrabhakar Kushwaha u32 porsr1, pinctl;
4131530e0bSPrabhakar Kushwaha u32 svr = get_svr();
4218c01445SPrabhakar Kushwaha #endif
4318c01445SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
4418c01445SPrabhakar Kushwaha
459f074e67SPrabhakar Kushwaha #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
4631530e0bSPrabhakar Kushwaha if (IS_SVR_REV(svr, 1, 0)) {
4718c01445SPrabhakar Kushwaha /*
4831530e0bSPrabhakar Kushwaha * There is T1040 SoC issue where NOR, FPGA are inaccessible
4931530e0bSPrabhakar Kushwaha * during NAND boot because IFC signals > IFC_AD7 are not
5031530e0bSPrabhakar Kushwaha * enabled. This workaround changes RCW source to make all
5131530e0bSPrabhakar Kushwaha * signals enabled.
5218c01445SPrabhakar Kushwaha */
5318c01445SPrabhakar Kushwaha porsr1 = in_be32(&gur->porsr1);
5431530e0bSPrabhakar Kushwaha pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
5531530e0bSPrabhakar Kushwaha | 0x24800000);
5631530e0bSPrabhakar Kushwaha out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
5731530e0bSPrabhakar Kushwaha pinctl);
5831530e0bSPrabhakar Kushwaha }
5918c01445SPrabhakar Kushwaha #endif
6018c01445SPrabhakar Kushwaha
6118c01445SPrabhakar Kushwaha /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
6218c01445SPrabhakar Kushwaha memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
6318c01445SPrabhakar Kushwaha
6418c01445SPrabhakar Kushwaha /* Update GD pointer */
6518c01445SPrabhakar Kushwaha gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
6618c01445SPrabhakar Kushwaha
67ce249d95STang Yuantian #ifdef CONFIG_DEEP_SLEEP
68ce249d95STang Yuantian /* disable the console if boot from deep sleep */
6900233528STang Yuantian if (is_warm_boot())
7000233528STang Yuantian fsl_dp_disable_console();
71ce249d95STang Yuantian #endif
7218c01445SPrabhakar Kushwaha /* compiler optimization barrier needed for GCC >= 3.4 */
7318c01445SPrabhakar Kushwaha __asm__ __volatile__("" : : : "memory");
7418c01445SPrabhakar Kushwaha
7518c01445SPrabhakar Kushwaha console_init_f();
7618c01445SPrabhakar Kushwaha
7718c01445SPrabhakar Kushwaha /* initialize selected port with appropriate baud rate */
7818c01445SPrabhakar Kushwaha sys_clk = get_board_sys_clk();
7918c01445SPrabhakar Kushwaha plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
8018c01445SPrabhakar Kushwaha uart_clk = sys_clk * plat_ratio / 2;
8118c01445SPrabhakar Kushwaha
8218c01445SPrabhakar Kushwaha NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
8318c01445SPrabhakar Kushwaha uart_clk / 16 / CONFIG_BAUDRATE);
8418c01445SPrabhakar Kushwaha
8518c01445SPrabhakar Kushwaha relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
8618c01445SPrabhakar Kushwaha }
8718c01445SPrabhakar Kushwaha
board_init_r(gd_t * gd,ulong dest_addr)8818c01445SPrabhakar Kushwaha void board_init_r(gd_t *gd, ulong dest_addr)
8918c01445SPrabhakar Kushwaha {
9018c01445SPrabhakar Kushwaha bd_t *bd;
9118c01445SPrabhakar Kushwaha
9218c01445SPrabhakar Kushwaha bd = (bd_t *)(gd + sizeof(gd_t));
9318c01445SPrabhakar Kushwaha memset(bd, 0, sizeof(bd_t));
9418c01445SPrabhakar Kushwaha gd->bd = bd;
9518c01445SPrabhakar Kushwaha bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
9618c01445SPrabhakar Kushwaha bd->bi_memsize = CONFIG_SYS_L3_SIZE;
9718c01445SPrabhakar Kushwaha
98cbcbf71bSSimon Glass arch_cpu_init();
9918c01445SPrabhakar Kushwaha get_clocks();
10018c01445SPrabhakar Kushwaha mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
10118c01445SPrabhakar Kushwaha CONFIG_SPL_RELOC_MALLOC_SIZE);
102ed4708aaSSumit Garg gd->flags |= GD_FLG_FULL_MALLOC_INIT;
10318c01445SPrabhakar Kushwaha
10418c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT
10518c01445SPrabhakar Kushwaha mmc_initialize(bd);
10618c01445SPrabhakar Kushwaha #endif
10718c01445SPrabhakar Kushwaha
10818c01445SPrabhakar Kushwaha /* relocate environment function pointers etc. */
10918c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT
11018c01445SPrabhakar Kushwaha nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
11118c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR);
11218c01445SPrabhakar Kushwaha #endif
11318c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT
11418c01445SPrabhakar Kushwaha mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
11518c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR);
11618c01445SPrabhakar Kushwaha #endif
11718c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_SPI_BOOT
118ea022a37SSimon Glass fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
11918c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR);
12018c01445SPrabhakar Kushwaha #endif
12118c01445SPrabhakar Kushwaha gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
122203e94f6SSimon Glass gd->env_valid = ENV_VALID;
12318c01445SPrabhakar Kushwaha
12418c01445SPrabhakar Kushwaha i2c_init_all();
12518c01445SPrabhakar Kushwaha
12618c01445SPrabhakar Kushwaha puts("\n\n");
12718c01445SPrabhakar Kushwaha
128f1683aa7SSimon Glass dram_init();
12918c01445SPrabhakar Kushwaha
13018c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT
13118c01445SPrabhakar Kushwaha mmc_boot();
13218c01445SPrabhakar Kushwaha #elif defined(CONFIG_SPL_SPI_BOOT)
133ea022a37SSimon Glass fsl_spi_boot();
13418c01445SPrabhakar Kushwaha #elif defined(CONFIG_SPL_NAND_BOOT)
13518c01445SPrabhakar Kushwaha nand_boot();
13618c01445SPrabhakar Kushwaha #endif
13718c01445SPrabhakar Kushwaha }
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