Searched hist:ffd06e0231ac3fd0c5810f39f6e23527948df1c7 (Results 1 – 8 of 8) sorted by relevance
/openbmc/u-boot/doc/ |
H A D | README.mpc85xx-spin-table | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | mp.h | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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H A D | mp.c | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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H A D | tlb.c | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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H A D | release.S | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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H A D | fdt.c | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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/openbmc/u-boot/arch/powerpc/include/asm/ |
H A D | config_mpc85xx.h | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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/openbmc/u-boot/ |
H A D | README | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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