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/openbmc/u-boot/doc/
H A DREADME.mpc85xx-spin-tableffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmp.hffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
H A Dmp.cffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
H A Dtlb.cffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
H A Drelease.Sffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
H A Dfdt.cffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dconfig_mpc85xx.hffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
/openbmc/u-boot/
H A DREADMEffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Oct 08 02:44:30 CDT 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>