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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_secure_boot.hfb4a2409b46c98672557bb07dec8e873bef1e23c Tue Mar 18 13:10:26 CDT 2014 Aneesh Bansal <aneesh.bansal@freescale.com> powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dstart.Sfb4a2409b46c98672557bb07dec8e873bef1e23c Tue Mar 18 13:10:26 CDT 2014 Aneesh Bansal <aneesh.bansal@freescale.com> powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
H A Dcpu_init.cfb4a2409b46c98672557bb07dec8e873bef1e23c Tue Mar 18 13:10:26 CDT 2014 Aneesh Bansal <aneesh.bansal@freescale.com> powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
/openbmc/u-boot/
H A DREADMEfb4a2409b46c98672557bb07dec8e873bef1e23c Tue Mar 18 13:10:26 CDT 2014 Aneesh Bansal <aneesh.bansal@freescale.com> powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>