Searched hist:b5b6b019 (Results 1 – 4 of 4) sorted by relevance
/openbmc/u-boot/arch/x86/include/asm/ |
H A D | pirq_routing.h | b5b6b019 Fri Apr 24 05:10:05 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: Support platform PIRQ routing On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
|
/openbmc/u-boot/arch/x86/lib/ |
H A D | pirq_routing.c | b5b6b019 Fri Apr 24 05:10:05 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: Support platform PIRQ routing On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
|
H A D | Makefile | b5b6b019 Fri Apr 24 05:10:05 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: Support platform PIRQ routing On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
|
/openbmc/u-boot/arch/x86/ |
H A D | Kconfig | b5b6b019 Fri Apr 24 05:10:05 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: Support platform PIRQ routing On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
|