1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4  *
5  * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h
6  */
7 
8 #ifndef _PIRQ_ROUTING_H_
9 #define _PIRQ_ROUTING_H_
10 
11 /*
12  * This is the maximum number on interrupt entries that a PCI device may have.
13  *   This is NOT the number of slots or devices in the system
14  *   This is NOT the number of entries in the PIRQ table
15  *
16  * This tells us that in the PIRQ table, we are going to have 4 link-bitmap
17  * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD.
18  *
19  * CAUTION: If you change this, PIRQ routing will not work correctly.
20  */
21 #define MAX_INTX_ENTRIES	4
22 
23 #define PIRQ_SIGNATURE		\
24 	(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
25 #define PIRQ_VERSION		0x0100
26 
27 struct __packed irq_info {
28 	u8 bus;			/* Bus number */
29 	u8 devfn;		/* Device and function number */
30 	struct __packed {
31 		u8 link;	/* IRQ line ID, 0=not routed */
32 		u16 bitmap;	/* Available IRQs */
33 	} irq[MAX_INTX_ENTRIES];
34 	u8 slot;		/* Slot number, 0=onboard */
35 	u8 rfu;
36 };
37 
38 struct __packed irq_routing_table {
39 	u32 signature;		/* PIRQ_SIGNATURE */
40 	u16 version;		/* PIRQ_VERSION */
41 	u16 size;		/* Table size in bytes */
42 	u8 rtr_bus;		/* busno of the interrupt router */
43 	u8 rtr_devfn;		/* devfn of the interrupt router */
44 	u16 exclusive_irqs;	/* IRQs devoted exclusively to PCI usage */
45 	u16 rtr_vendor;		/* Vendor ID of the interrupt router */
46 	u16 rtr_device;		/* Device ID of the interrupt router */
47 	u32 miniport_data;
48 	u8 rfu[11];
49 	u8 checksum;		/* Modulo 256 checksum must give zero */
50 	struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
51 };
52 
53 /**
54  * get_irq_slot_count() - Get the number of entries in the irq_info table
55  *
56  * This calculates the number of entries for the irq_info table.
57  *
58  * @rt:		pointer to the base address of the struct irq_info
59  * @return:	number of entries
60  */
get_irq_slot_count(struct irq_routing_table * rt)61 static inline int get_irq_slot_count(struct irq_routing_table *rt)
62 {
63 	return (rt->size - 32) / sizeof(struct irq_info);
64 }
65 
66 /**
67  * pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC
68  *
69  * This function checks whether an IRQ is routed to 8259 PIC for a given link.
70  *
71  * Note: this function should be provided by the platform codes, as the
72  * implementation of interrupt router may be different.
73  *
74  * @dev:	irq router's udevice
75  * @link:	link number which represents a PIRQ
76  * @irq:	the 8259 IRQ number
77  * @return:	true if the irq is already routed to 8259 for a given link,
78  *		false elsewise
79  */
80 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq);
81 
82 /**
83  * pirq_translate_link() - Translate a link value
84  *
85  * This function translates a platform-specific link value to a link number.
86  * On Intel platforms, the link value is normally a offset into the PCI
87  * configuration space into the legacy bridge.
88  *
89  * Note: this function should be provided by the platform codes, as the
90  * implementation of interrupt router may be different.
91  *
92  * @dev:	irq router's udevice
93  * @link:	platform-specific link value
94  * @return:	link number which represents a PIRQ
95  */
96 int pirq_translate_link(struct udevice *dev, int link);
97 
98 /**
99  * pirq_assign_irq() - Assign an IRQ to a PIRQ link
100  *
101  * This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to
102  * the 8259 PIC.
103  *
104  * Note: this function should be provided by the platform codes, as the
105  * implementation of interrupt router may be different.
106  *
107  * @dev:	irq router's udevice
108  * @link:	link number which represents a PIRQ
109  * @irq:	IRQ to which the PIRQ is routed
110  */
111 void pirq_assign_irq(struct udevice *dev, int link, u8 irq);
112 
113 /**
114  * pirq_route_irqs() - Route PIRQs to 8259 PIC
115  *
116  * This function configures all PCI devices' interrupt pins and maps them to
117  * PIRQs and finally 8259 PIC. The routed irq number is written to interrupt
118  * line register in the configuration space of the PCI device for OS to use.
119  * The configuration source is taken from a struct irq_info table, the format
120  * of which is defined in PIRQ routing table spec and PCI BIOS spec.
121  *
122  * @dev:	irq router's udevice
123  * @irq:	pointer to the base address of the struct irq_info
124  * @num:	number of entries in the struct irq_info
125  */
126 void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num);
127 
128 /**
129  * copy_pirq_routing_table() - Copy a PIRQ routing table
130  *
131  * This helper function copies the given PIRQ routing table to a given address.
132  * Before copying, it does several sanity tests against the PIRQ routing table.
133  * It also fixes up the table checksum and align the given address to a 16 byte
134  * boundary to meet the PIRQ routing table spec requirements.
135  *
136  * @addr:	address to store the copied PIRQ routing table
137  * @rt:		pointer to the PIRQ routing table to copy from
138  * @return:	end address of the copied PIRQ routing table
139  */
140 u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt);
141 
142 #endif /* _PIRQ_ROUTING_H_ */
143