Searched hist:"92 bd868f" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qmp-pcs-v5_20.h | 92bd868f Fri Mar 17 01:38:34 CDT 2023 Rohit Agarwal <quic_rohiagar@quicinc.com> phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY
The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| H A D | phy-qcom-qmp-qserdes-txrx-v5_20.h | 92bd868f Fri Mar 17 01:38:34 CDT 2023 Rohit Agarwal <quic_rohiagar@quicinc.com> phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY
The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| H A D | phy-qcom-qmp-pcs-pcie-v5_20.h | 92bd868f Fri Mar 17 01:38:34 CDT 2023 Rohit Agarwal <quic_rohiagar@quicinc.com> phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY
The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| H A D | phy-qcom-qmp-pcie.c | 92bd868f Fri Mar 17 01:38:34 CDT 2023 Rohit Agarwal <quic_rohiagar@quicinc.com> phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY
The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|