Searched hist:"672 e5598" (Results 1 – 2 of 2) sorted by relevance
/openbmc/u-boot/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_db.c | 672e5598 Wed Jan 17 22:16:10 CST 2018 Chris Packham <judge.packham@gmail.com> ddr: marvell: update ddr controller init and freq Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs currently being supplied by Marvell. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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H A D | ddr3_training.c | 672e5598 Wed Jan 17 22:16:10 CST 2018 Chris Packham <judge.packham@gmail.com> ddr: marvell: update ddr controller init and freq Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs currently being supplied by Marvell. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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