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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_db.c672e5598 Wed Jan 17 22:16:10 CST 2018 Chris Packham <judge.packham@gmail.com> ddr: marvell: update ddr controller init and freq

Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
H A Dddr3_training.c672e5598 Wed Jan 17 22:16:10 CST 2018 Chris Packham <judge.packham@gmail.com> ddr: marvell: update ddr controller init and freq

Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>