Searched hist:"35817 d34" (Results 1 – 3 of 3) sorted by relevance
/openbmc/linux/drivers/pinctrl/sunxi/ |
H A D | pinctrl-sun8i-v3s.c | 35817d34 Fri Mar 16 09:02:09 CDT 2018 Icenowy Zheng <icenowy@aosc.io> pinctrl: sunxi: change irq_bank_base to irq_bank_map
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 35817d34 Fri Mar 16 09:02:09 CDT 2018 Icenowy Zheng <icenowy@aosc.io> pinctrl: sunxi: change irq_bank_base to irq_bank_map The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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H A D | pinctrl-sun8i-a33.c | 35817d34 Fri Mar 16 09:02:09 CDT 2018 Icenowy Zheng <icenowy@aosc.io> pinctrl: sunxi: change irq_bank_base to irq_bank_map
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 35817d34 Fri Mar 16 09:02:09 CDT 2018 Icenowy Zheng <icenowy@aosc.io> pinctrl: sunxi: change irq_bank_base to irq_bank_map The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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H A D | pinctrl-sunxi.h | 35817d34 Fri Mar 16 09:02:09 CDT 2018 Icenowy Zheng <icenowy@aosc.io> pinctrl: sunxi: change irq_bank_base to irq_bank_map
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 35817d34 Fri Mar 16 09:02:09 CDT 2018 Icenowy Zheng <icenowy@aosc.io> pinctrl: sunxi: change irq_bank_base to irq_bank_map The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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