15f910777SMaxime Ripard /*
25f910777SMaxime Ripard * Allwinner A1X SoCs pinctrl driver.
35f910777SMaxime Ripard *
45f910777SMaxime Ripard * Copyright (C) 2012 Maxime Ripard
55f910777SMaxime Ripard *
65f910777SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com>
75f910777SMaxime Ripard *
85f910777SMaxime Ripard * This file is licensed under the terms of the GNU General Public
95f910777SMaxime Ripard * License version 2. This program is licensed "as is" without any
105f910777SMaxime Ripard * warranty of any kind, whether express or implied.
115f910777SMaxime Ripard */
125f910777SMaxime Ripard
135f910777SMaxime Ripard #ifndef __PINCTRL_SUNXI_H
145f910777SMaxime Ripard #define __PINCTRL_SUNXI_H
155f910777SMaxime Ripard
165f910777SMaxime Ripard #include <linux/kernel.h>
175f910777SMaxime Ripard #include <linux/spinlock.h>
185f910777SMaxime Ripard
195f910777SMaxime Ripard #define PA_BASE 0
205f910777SMaxime Ripard #define PB_BASE 32
215f910777SMaxime Ripard #define PC_BASE 64
225f910777SMaxime Ripard #define PD_BASE 96
235f910777SMaxime Ripard #define PE_BASE 128
245f910777SMaxime Ripard #define PF_BASE 160
255f910777SMaxime Ripard #define PG_BASE 192
265f910777SMaxime Ripard #define PH_BASE 224
275f910777SMaxime Ripard #define PI_BASE 256
285f910777SMaxime Ripard #define PL_BASE 352
295f910777SMaxime Ripard #define PM_BASE 384
304f6bd5cfSMaxime Ripard #define PN_BASE 416
315f910777SMaxime Ripard
32d10acc63SMaxime Ripard #define SUNXI_PINCTRL_PIN(bank, pin) \
33d10acc63SMaxime Ripard PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
345f910777SMaxime Ripard
355f910777SMaxime Ripard #define SUNXI_PIN_NAME_MAX_LEN 5
365f910777SMaxime Ripard
375f910777SMaxime Ripard #define BANK_MEM_SIZE 0x24
385f910777SMaxime Ripard #define MUX_REGS_OFFSET 0x0
390bb95ae2SSamuel Holland #define MUX_FIELD_WIDTH 4
405f910777SMaxime Ripard #define DATA_REGS_OFFSET 0x10
410bb95ae2SSamuel Holland #define DATA_FIELD_WIDTH 1
425f910777SMaxime Ripard #define DLEVEL_REGS_OFFSET 0x14
430bb95ae2SSamuel Holland #define DLEVEL_FIELD_WIDTH 2
445f910777SMaxime Ripard #define PULL_REGS_OFFSET 0x1c
450bb95ae2SSamuel Holland #define PULL_FIELD_WIDTH 2
465f910777SMaxime Ripard
47*0569af48SSamuel Holland #define D1_BANK_MEM_SIZE 0x30
48*0569af48SSamuel Holland #define D1_DLEVEL_FIELD_WIDTH 4
49*0569af48SSamuel Holland #define D1_PULL_REGS_OFFSET 0x24
50*0569af48SSamuel Holland
515f910777SMaxime Ripard #define PINS_PER_BANK 32
525f910777SMaxime Ripard
53aebdc8abSMaxime Ripard #define IRQ_PER_BANK 32
545f910777SMaxime Ripard
555f910777SMaxime Ripard #define IRQ_CFG_REG 0x200
565f910777SMaxime Ripard #define IRQ_CFG_IRQ_PER_REG 8
575f910777SMaxime Ripard #define IRQ_CFG_IRQ_BITS 4
585f910777SMaxime Ripard #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
595f910777SMaxime Ripard #define IRQ_CTRL_REG 0x210
605f910777SMaxime Ripard #define IRQ_CTRL_IRQ_PER_REG 32
615f910777SMaxime Ripard #define IRQ_CTRL_IRQ_BITS 1
625f910777SMaxime Ripard #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
635f910777SMaxime Ripard #define IRQ_STATUS_REG 0x214
645f910777SMaxime Ripard #define IRQ_STATUS_IRQ_PER_REG 32
655f910777SMaxime Ripard #define IRQ_STATUS_IRQ_BITS 1
665f910777SMaxime Ripard #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
675f910777SMaxime Ripard
687c926492SMaxime Ripard #define IRQ_DEBOUNCE_REG 0x218
697c926492SMaxime Ripard
70aebdc8abSMaxime Ripard #define IRQ_MEM_SIZE 0x20
71aebdc8abSMaxime Ripard
725f910777SMaxime Ripard #define IRQ_EDGE_RISING 0x00
735f910777SMaxime Ripard #define IRQ_EDGE_FALLING 0x01
745f910777SMaxime Ripard #define IRQ_LEVEL_HIGH 0x02
755f910777SMaxime Ripard #define IRQ_LEVEL_LOW 0x03
765f910777SMaxime Ripard #define IRQ_EDGE_BOTH 0x04
775f910777SMaxime Ripard
78402bfb3cSChen-Yu Tsai #define GRP_CFG_REG 0x300
79402bfb3cSChen-Yu Tsai
80402bfb3cSChen-Yu Tsai #define IO_BIAS_MASK GENMASK(3, 0)
81402bfb3cSChen-Yu Tsai
82ef6d24ccSHans de Goede #define SUN4I_FUNC_INPUT 0
83ef6d24ccSHans de Goede #define SUN4I_FUNC_IRQ 6
84ef6d24ccSHans de Goede
85858f559fSMaxime Ripard #define PINCTRL_SUN5I_A10S BIT(1)
86858f559fSMaxime Ripard #define PINCTRL_SUN5I_A13 BIT(2)
87858f559fSMaxime Ripard #define PINCTRL_SUN5I_GR8 BIT(3)
884924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31 BIT(4)
894924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31S BIT(5)
9088798ba2SIcenowy Zheng #define PINCTRL_SUN4I_A10 BIT(6)
9188798ba2SIcenowy Zheng #define PINCTRL_SUN7I_A20 BIT(7)
9288798ba2SIcenowy Zheng #define PINCTRL_SUN8I_R40 BIT(8)
93fb18f188SIcenowy Zheng #define PINCTRL_SUN8I_V3 BIT(9)
94fb18f188SIcenowy Zheng #define PINCTRL_SUN8I_V3S BIT(10)
95*0569af48SSamuel Holland /* Variants below here have an updated register layout. */
96*0569af48SSamuel Holland #define PINCTRL_SUN20I_D1 BIT(11)
97858f559fSMaxime Ripard
98cc62383fSOndrej Jirman #define PIO_POW_MOD_SEL_REG 0x340
9988df36f2SSamuel Holland #define PIO_POW_MOD_CTL_REG 0x344
100cc62383fSOndrej Jirman
101f7275345SOndrej Jirman enum sunxi_desc_bias_voltage {
102f7275345SOndrej Jirman BIAS_VOLTAGE_NONE,
103f7275345SOndrej Jirman /*
104f7275345SOndrej Jirman * Bias voltage configuration is done through
105f7275345SOndrej Jirman * Pn_GRP_CONFIG registers, as seen on A80 SoC.
106f7275345SOndrej Jirman */
107f7275345SOndrej Jirman BIAS_VOLTAGE_GRP_CONFIG,
108cc62383fSOndrej Jirman /*
109cc62383fSOndrej Jirman * Bias voltage is set through PIO_POW_MOD_SEL_REG
110cc62383fSOndrej Jirman * register, as seen on H6 SoC, for example.
111cc62383fSOndrej Jirman */
112cc62383fSOndrej Jirman BIAS_VOLTAGE_PIO_POW_MODE_SEL,
11388df36f2SSamuel Holland /*
11488df36f2SSamuel Holland * Bias voltage is set through PIO_POW_MOD_SEL_REG
11588df36f2SSamuel Holland * and PIO_POW_MOD_CTL_REG register, as seen on
11688df36f2SSamuel Holland * A100 and D1 SoC, for example.
11788df36f2SSamuel Holland */
11888df36f2SSamuel Holland BIAS_VOLTAGE_PIO_POW_MODE_CTL,
119f7275345SOndrej Jirman };
120f7275345SOndrej Jirman
1215f910777SMaxime Ripard struct sunxi_desc_function {
122578db85fSMaxime Ripard unsigned long variant;
1235f910777SMaxime Ripard const char *name;
1245f910777SMaxime Ripard u8 muxval;
1256e1c3023SMaxime Ripard u8 irqbank;
1265f910777SMaxime Ripard u8 irqnum;
1275f910777SMaxime Ripard };
1285f910777SMaxime Ripard
1295f910777SMaxime Ripard struct sunxi_desc_pin {
1305f910777SMaxime Ripard struct pinctrl_pin_desc pin;
131578db85fSMaxime Ripard unsigned long variant;
1325f910777SMaxime Ripard struct sunxi_desc_function *functions;
1335f910777SMaxime Ripard };
1345f910777SMaxime Ripard
1355f910777SMaxime Ripard struct sunxi_pinctrl_desc {
1365f910777SMaxime Ripard const struct sunxi_desc_pin *pins;
1375f910777SMaxime Ripard int npins;
1385f910777SMaxime Ripard unsigned pin_base;
1398966ada2SMaxime Ripard unsigned irq_banks;
14035817d34SIcenowy Zheng const unsigned int *irq_bank_map;
141ef6d24ccSHans de Goede bool irq_read_needs_mux;
142aae842a3SMaxime Ripard bool disable_strict_mode;
143f7275345SOndrej Jirman enum sunxi_desc_bias_voltage io_bias_cfg_variant;
1445f910777SMaxime Ripard };
1455f910777SMaxime Ripard
1465f910777SMaxime Ripard struct sunxi_pinctrl_function {
1475f910777SMaxime Ripard const char *name;
1485f910777SMaxime Ripard const char **groups;
1495f910777SMaxime Ripard unsigned ngroups;
1505f910777SMaxime Ripard };
1515f910777SMaxime Ripard
1525f910777SMaxime Ripard struct sunxi_pinctrl_group {
1535f910777SMaxime Ripard const char *name;
1545f910777SMaxime Ripard unsigned pin;
1555f910777SMaxime Ripard };
1565f910777SMaxime Ripard
1579a2a566aSMaxime Ripard struct sunxi_pinctrl_regulator {
1589a2a566aSMaxime Ripard struct regulator *regulator;
1599a2a566aSMaxime Ripard refcount_t refcount;
1609a2a566aSMaxime Ripard };
1619a2a566aSMaxime Ripard
1625f910777SMaxime Ripard struct sunxi_pinctrl {
1635f910777SMaxime Ripard void __iomem *membase;
1645f910777SMaxime Ripard struct gpio_chip *chip;
1655f910777SMaxime Ripard const struct sunxi_pinctrl_desc *desc;
1665f910777SMaxime Ripard struct device *dev;
167ca443844SChen-Yu Tsai struct sunxi_pinctrl_regulator regulators[9];
1685f910777SMaxime Ripard struct irq_domain *domain;
1695f910777SMaxime Ripard struct sunxi_pinctrl_function *functions;
1705f910777SMaxime Ripard unsigned nfunctions;
1715f910777SMaxime Ripard struct sunxi_pinctrl_group *groups;
1725f910777SMaxime Ripard unsigned ngroups;
173aebdc8abSMaxime Ripard int *irq;
174aebdc8abSMaxime Ripard unsigned *irq_array;
175f658ed36SJulia Cartwright raw_spinlock_t lock;
1765f910777SMaxime Ripard struct pinctrl_dev *pctl_dev;
177578db85fSMaxime Ripard unsigned long variant;
178622b681eSSamuel Holland u32 bank_mem_size;
179622b681eSSamuel Holland u32 pull_regs_offset;
180622b681eSSamuel Holland u32 dlevel_field_width;
1815f910777SMaxime Ripard };
1825f910777SMaxime Ripard
1835f910777SMaxime Ripard #define SUNXI_PIN(_pin, ...) \
1845f910777SMaxime Ripard { \
1855f910777SMaxime Ripard .pin = _pin, \
1865f910777SMaxime Ripard .functions = (struct sunxi_desc_function[]){ \
1875f910777SMaxime Ripard __VA_ARGS__, { } }, \
1885f910777SMaxime Ripard }
1895f910777SMaxime Ripard
190578db85fSMaxime Ripard #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
191578db85fSMaxime Ripard { \
192578db85fSMaxime Ripard .pin = _pin, \
193578db85fSMaxime Ripard .variant = _variant, \
194578db85fSMaxime Ripard .functions = (struct sunxi_desc_function[]){ \
195578db85fSMaxime Ripard __VA_ARGS__, { } }, \
196578db85fSMaxime Ripard }
197578db85fSMaxime Ripard
1985f910777SMaxime Ripard #define SUNXI_FUNCTION(_val, _name) \
1995f910777SMaxime Ripard { \
2005f910777SMaxime Ripard .name = _name, \
2015f910777SMaxime Ripard .muxval = _val, \
2025f910777SMaxime Ripard }
2035f910777SMaxime Ripard
204578db85fSMaxime Ripard #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
205578db85fSMaxime Ripard { \
206578db85fSMaxime Ripard .name = _name, \
207578db85fSMaxime Ripard .muxval = _val, \
208578db85fSMaxime Ripard .variant = _variant, \
209578db85fSMaxime Ripard }
210578db85fSMaxime Ripard
2115f910777SMaxime Ripard #define SUNXI_FUNCTION_IRQ(_val, _irq) \
2125f910777SMaxime Ripard { \
2135f910777SMaxime Ripard .name = "irq", \
2145f910777SMaxime Ripard .muxval = _val, \
2155f910777SMaxime Ripard .irqnum = _irq, \
2165f910777SMaxime Ripard }
2175f910777SMaxime Ripard
2186e1c3023SMaxime Ripard #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
2196e1c3023SMaxime Ripard { \
2206e1c3023SMaxime Ripard .name = "irq", \
2216e1c3023SMaxime Ripard .muxval = _val, \
2226e1c3023SMaxime Ripard .irqbank = _bank, \
2236e1c3023SMaxime Ripard .irqnum = _irq, \
2246e1c3023SMaxime Ripard }
2256e1c3023SMaxime Ripard
sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc * desc,u8 bank)22629dfc6bbSIcenowy Zheng static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
22729dfc6bbSIcenowy Zheng {
22835817d34SIcenowy Zheng if (!desc->irq_bank_map)
22935817d34SIcenowy Zheng return bank;
23035817d34SIcenowy Zheng else
23135817d34SIcenowy Zheng return desc->irq_bank_map[bank];
23229dfc6bbSIcenowy Zheng }
23329dfc6bbSIcenowy Zheng
sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)2344b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
2354b0d6c5aSIcenowy Zheng u16 irq)
2365f910777SMaxime Ripard {
237aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK;
238aebdc8abSMaxime Ripard u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
239aebdc8abSMaxime Ripard
24029dfc6bbSIcenowy Zheng return IRQ_CFG_REG +
24129dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
2425f910777SMaxime Ripard }
2435f910777SMaxime Ripard
sunxi_irq_cfg_offset(u16 irq)2445f910777SMaxime Ripard static inline u32 sunxi_irq_cfg_offset(u16 irq)
2455f910777SMaxime Ripard {
2465f910777SMaxime Ripard u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
2475f910777SMaxime Ripard return irq_num * IRQ_CFG_IRQ_BITS;
2485f910777SMaxime Ripard }
2495f910777SMaxime Ripard
sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)2504b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
251aebdc8abSMaxime Ripard {
25229dfc6bbSIcenowy Zheng return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
253aebdc8abSMaxime Ripard }
254aebdc8abSMaxime Ripard
sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)2554b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
2564b0d6c5aSIcenowy Zheng u16 irq)
2575f910777SMaxime Ripard {
258aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK;
259aebdc8abSMaxime Ripard
2604b0d6c5aSIcenowy Zheng return sunxi_irq_ctrl_reg_from_bank(desc, bank);
2615f910777SMaxime Ripard }
2625f910777SMaxime Ripard
sunxi_irq_ctrl_offset(u16 irq)2635f910777SMaxime Ripard static inline u32 sunxi_irq_ctrl_offset(u16 irq)
2645f910777SMaxime Ripard {
2655f910777SMaxime Ripard u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
2665f910777SMaxime Ripard return irq_num * IRQ_CTRL_IRQ_BITS;
2675f910777SMaxime Ripard }
2685f910777SMaxime Ripard
sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)2694b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
2707c926492SMaxime Ripard {
27129dfc6bbSIcenowy Zheng return IRQ_DEBOUNCE_REG +
27229dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
2737c926492SMaxime Ripard }
2747c926492SMaxime Ripard
sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)2754b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
276aebdc8abSMaxime Ripard {
27729dfc6bbSIcenowy Zheng return IRQ_STATUS_REG +
27829dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
279aebdc8abSMaxime Ripard }
280aebdc8abSMaxime Ripard
sunxi_irq_status_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)2814b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
2824b0d6c5aSIcenowy Zheng u16 irq)
2835f910777SMaxime Ripard {
284aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK;
285aebdc8abSMaxime Ripard
2864b0d6c5aSIcenowy Zheng return sunxi_irq_status_reg_from_bank(desc, bank);
2875f910777SMaxime Ripard }
2885f910777SMaxime Ripard
sunxi_irq_status_offset(u16 irq)2895f910777SMaxime Ripard static inline u32 sunxi_irq_status_offset(u16 irq)
2905f910777SMaxime Ripard {
2915f910777SMaxime Ripard u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
2925f910777SMaxime Ripard return irq_num * IRQ_STATUS_IRQ_BITS;
2935f910777SMaxime Ripard }
2945f910777SMaxime Ripard
sunxi_grp_config_reg(u16 pin)295402bfb3cSChen-Yu Tsai static inline u32 sunxi_grp_config_reg(u16 pin)
296402bfb3cSChen-Yu Tsai {
297402bfb3cSChen-Yu Tsai u8 bank = pin / PINS_PER_BANK;
298402bfb3cSChen-Yu Tsai
299402bfb3cSChen-Yu Tsai return GRP_CFG_REG + bank * 0x4;
300402bfb3cSChen-Yu Tsai }
301402bfb3cSChen-Yu Tsai
302578db85fSMaxime Ripard int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
303578db85fSMaxime Ripard const struct sunxi_pinctrl_desc *desc,
304578db85fSMaxime Ripard unsigned long variant);
305578db85fSMaxime Ripard
306578db85fSMaxime Ripard #define sunxi_pinctrl_init(_dev, _desc) \
307578db85fSMaxime Ripard sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
3082284ba6bSMaxime Ripard
3095f910777SMaxime Ripard #endif /* __PINCTRL_SUNXI_H */
310