/openbmc/linux/Documentation/devicetree/bindings/rtc/ |
H A D | xlnx,zynqmp-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock. 11 The RTC controller has separate IRQ lines for seconds and alarm. 14 - Michal Simek <michal.simek@amd.com> 17 - $ref: rtc.yaml# 21 const: xlnx,zynqmp-rtc 29 clock-names: [all …]
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/openbmc/qemu/include/hw/arm/ |
H A D | xlnx-zynqmp.h | 24 #include "hw/net/xlnx-zynqmp-can.h" 25 #include "hw/ide/ahci-sysbus.h" 29 #include "hw/dma/xlnx-zdma.h" 31 #include "hw/intc/xlnx-zynqmp-ipi.h" 32 #include "hw/rtc/xlnx-zynqmp-rtc.h" 38 #include "hw/nvram/xlnx-bbram.h" 39 #include "hw/nvram/xlnx-zynqmp-efuse.h" 40 #include "hw/or-irq.h" 41 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" 42 #include "hw/misc/xlnx-zynqmp-crf.h" [all …]
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/openbmc/linux/arch/arm64/boot/dts/xilinx/ |
H A D | zynqmp-zc1751-xm017-dc3.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/phy/phy.h> 17 model = "ZynqMP zc1751-xm017-dc3 RevA"; 18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 25 rtc0 = &rtc; [all …]
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H A D | zynqmp-zc1751-xm018-dc4.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4 5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 16 model = "ZynqMP zc1751-xm018-dc4"; 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 26 rtc0 = &rtc; 34 stdout-path = "serial0:115200n8"; [all …]
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H A D | zynqmp-zc1751-xm016-dc2.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 /dts-v1/; 13 #include "zynqmp.dtsi" 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 19 model = "ZynqMP zc1751-xm016-dc2 RevA"; [all …]
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H A D | zynqmp-zc1751-xm015-dc1.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 /dts-v1/; 13 #include "zynqmp.dtsi" 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> [all …]
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H A D | zynqmp-sm-k26-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A 5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/phy/phy.h> 17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> [all …]
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H A D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 #include <dt-bindings/interrupt-controller/irq.h> 19 #include <dt-bindings/power/xlnx-zynqmp-power.h> 20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 23 compatible = "xlnx,zynqmp"; [all …]
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H A D | zynqmp-zcu104-revC.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * dts file for Xilinx ZynqMP ZCU104 5 * (C) Copyright 2017 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 /dts-v1/; 13 #include "zynqmp.dtsi" 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17 #include <dt-bindings/phy/phy.h> [all …]
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H A D | zynqmp-zcu104-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU104 5 * (C) Copyright 2017 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 /dts-v1/; 13 #include "zynqmp.dtsi" 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17 #include <dt-bindings/phy/phy.h> [all …]
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H A D | zynqmp-zcu100-revC.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU100 revC 5 * (C) Copyright 2016 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 12 /dts-v1/; 14 #include "zynqmp.dtsi" 15 #include "zynqmp-clk-ccf.dtsi" 16 #include <dt-bindings/input/input.h> 17 #include <dt-bindings/interrupt-controller/irq.h> 18 #include <dt-bindings/gpio/gpio.h> [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | zynqmp-zc1751-xm017-dc3.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3 5 * (C) Copyright 2016 - 2018, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 16 model = "ZynqMP zc1751-xm017-dc3 RevA"; 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 25 rtc0 = &rtc; 34 stdout-path = "serial0:115200n8"; [all …]
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H A D | zynqmp-zc1751-xm016-dc2.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2 5 * (C) Copyright 2015 - 2018, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 16 model = "ZynqMP zc1751-xm016-dc2 RevA"; 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 25 rtc0 = &rtc; 35 stdout-path = "serial0:115200n8"; [all …]
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H A D | zynqmp-zc1751-xm018-dc4.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4 5 * (C) Copyright 2015 - 2018, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 16 model = "ZynqMP zc1751-xm018-dc4"; 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 29 rtc0 = &rtc; 37 stdout-path = "serial0:115200n8"; [all …]
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H A D | zynqmp-zc1751-xm015-dc1.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1 5 * (C) Copyright 2015 - 2018, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 16 model = "ZynqMP zc1751-xm015-dc1 RevA"; 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 25 rtc0 = &rtc; 33 stdout-path = "serial0:115200n8"; [all …]
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H A D | zynqmp-zcu104-revC.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU104 5 * (C) Copyright 2017 - 2018, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/phy/phy.h> 18 model = "ZynqMP ZCU104 RevC"; 19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; [all …]
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H A D | zynqmp-zcu104-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU104 5 * (C) Copyright 2017 - 2018, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/phy/phy.h> 18 model = "ZynqMP ZCU104 RevA"; 19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; [all …]
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H A D | zynqmp-zcu100-revC.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU100 revC 5 * (C) Copyright 2016 - 2018, Xilinx, Inc. 11 /dts-v1/; 13 #include "zynqmp.dtsi" 14 #include "zynqmp-clk.dtsi" 15 #include <dt-bindings/input/input.h> 16 #include <dt-bindings/interrupt-controller/irq.h> 17 #include <dt-bindings/gpio/gpio.h> 18 #include <dt-bindings/phy/phy.h> [all …]
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H A D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP 5 * (C) Copyright 2014 - 2015, Xilinx, Inc. 16 compatible = "xlnx,zynqmp"; 17 #address-cells = <2>; 18 #size-cells = <2>; 21 #address-cells = <1>; 22 #size-cells = <0>; 25 compatible = "arm,cortex-a53", "arm,armv8"; 27 enable-method = "psci"; [all …]
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H A D | zynqmp-zcu111-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU111 5 * (C) Copyright 2017 - 2018, Xilinx, Inc. 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/phy/phy.h> 19 model = "ZynqMP ZCU111 RevA"; [all …]
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H A D | zynqmp-zcu106-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP ZCU106 10 /dts-v1/; 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/phy/phy.h> 19 model = "ZynqMP ZCU106 RevA"; 20 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; [all …]
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/openbmc/qemu/hw/rtc/ |
H A D | meson.build | 6 system_ss.add(when: ['CONFIG_ISA_BUS', 'CONFIG_M48T59'], if_true: files('m48t59-isa.c')) 7 system_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-rtc.c')) 10 system_ss.add(when: 'CONFIG_SUN4V_RTC', if_true: files('sun4v-rtc.c')) 14 system_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-rtc.c'))
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H A D | trace-events | 3 # allwinner-rtc.c 7 # sun4v-rtc.c 11 # xlnx-zynqmp-rtc.c 12 … year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" 26 ds1338_recv(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] -> 0x%02" PRIx8 27 ds1338_send(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] <- 0x%02" PRIx8
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H A D | xlnx-zynqmp-rtc.c | 2 * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). 6 * Written-by: Alistair Francis <alistair.francis@xilinx.com> 36 #include "sysemu/rtc.h" 38 #include "hw/rtc/xlnx-zynqmp-rtc.h" 47 bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK]; in rtc_int_update_irq() 48 qemu_set_irq(s->irq_rtc_int, pending); in rtc_int_update_irq() 53 bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK]; in addr_error_int_update_irq() 54 qemu_set_irq(s->irq_addr_error_int, pending); in addr_error_int_update_irq() 60 return s->tick_offset + now / NANOSECONDS_PER_SECOND; in rtc_get_count() 65 XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); in current_time_postr() [all …]
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/openbmc/linux/drivers/rtc/ |
H A D | rtc-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0 16 #include <linux/rtc.h> 18 /* RTC Registers */ 47 #define RTC_MIN_OFFSET -32768000 51 struct rtc_device *rtc; member 71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time() 74 * Clear the rtc interrupt status register after setting the in xlnx_rtc_set_time() 77 * that one second has not elapsed yet since RTC was set and in xlnx_rtc_set_time() 81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time() 92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time() [all …]
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