Searched +full:zynqmp +full:- +full:ocmc +full:- +full:1 (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx Zynqmp OCM(On-Chip Memory) Controller10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>14 The OCM supports 64-bit wide ECC functionality to detect multi-bit errors15 and recover from a single-bit memory fault.On a write, if all bytes are17 the write-data that is written into the data RAM. If one or more bytes are[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Xilinx ZynqMP OCM ECC Driver70 #define EDAC_DEVICE "ZynqMP-OCM"73 * struct ecc_error_info - ECC error log information75 * @fault_lo: Generated fault data (lower 32-bit)76 * @fault_hi: Generated fault data (upper 32-bit)85 * struct ecc_status - ECC status information to report99 * struct edac_priv - OCM private instance data125 * get_error_info - Get the current ECC error info136 p->ce_cnt++; in get_error_info()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP5 * (C) Copyright 2014 - 2015, Xilinx, Inc.16 compatible = "xlnx,zynqmp";17 #address-cells = <2>;18 #size-cells = <2>;21 #address-cells = <1>;22 #size-cells = <0>;25 compatible = "arm,cortex-a53", "arm,armv8";27 enable-method = "psci";[all …]
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