Searched +full:zynq +full:- +full:pinctrl (Results 1 – 25 of 30) sorted by relevance
12
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx Zynq Pinctrl10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>13 Please refer to pinctrl-bindings.txt in this directory for details of the14 common pinctrl bindings used by client devices, including the meaning of the17 Zynq's pin configuration nodes act as a container for an arbitrary number of21 parameters, such as pull-up, slew rate, etc.[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx6 /dts-v1/;7 /include/ "zynq-7000.dtsi"11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";25 stdout-path = "serial0:115200n8";29 compatible = "usb-nop-xceiv";30 #phy-cells = <0>;35 ps-clk-frequency = <33333333>;40 phy-mode = "rgmii-id";[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx6 /dts-v1/;7 #include "zynq-7000.dtsi"11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";27 stdout-path = "serial0:115200n8";31 compatible = "usb-nop-xceiv";32 #phy-cells = <0>;37 ps-clk-frequency = <33333333>;42 phy-mode = "rgmii-id";[all …]
1 // SPDX-License-Identifier: GPL-2.05 /dts-v1/;6 /include/ "zynq-7000.dtsi"10 compatible = "ebang,ebaz4205", "xlnx,zynq-7000";23 stdout-path = "serial0:115200n8";28 ps-clk-frequency = <33333333>;29 fclk-enable = <8>;34 phy-mode = "mii";35 phy-handle = <&phy>;38 assigned-clocks = <&clkc 18>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx6 /dts-v1/;7 #include "zynq-7000.dtsi"8 #include <dt-bindings/gpio/gpio.h>12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";28 stdout-path = "serial0:115200n8";31 gpio-keys {32 compatible = "gpio-keys";34 switch-14 {[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx7 #address-cells = <1>;8 #size-cells = <1>;9 compatible = "xlnx,zynq-7000";12 #address-cells = <1>;13 #size-cells = <0>;16 compatible = "arm,cortex-a9";20 clock-latency = <1000>;21 cpu0-supply = <®ulator_vccpint>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2011 - 2015 Xilinx6 /dts-v1/;7 #include "zynq-7000.dtsi"11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";28 stdout-path = "serial0:115200n8";32 compatible = "usb-nop-xceiv";33 #phy-cells = <0>;38 ps-clk-frequency = <33333333>;43 phy-mode = "rgmii-id";[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Xilinx Zynq 7000 DTSI4 * Describes the hardware common to all Zynq 7000-based boards.6 * Copyright (C) 2011 - 2015 Xilinx10 #address-cells = <1>;11 #size-cells = <1>;12 compatible = "xlnx,zynq-7000";15 #address-cells = <1>;16 #size-cells = <0>;19 compatible = "arm,cortex-a9";[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2011 - 2015 Xilinx6 /dts-v1/;7 #include "zynq-7000.dtsi"11 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";28 stdout-path = "serial0:115200n8";31 gpio-keys {32 compatible = "gpio-keys";38 wakeup-source;45 wakeup-source;[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2014 - 2015, Xilinx, Inc.17 #address-cells = <2>;18 #size-cells = <2>;21 #address-cells = <1>;22 #size-cells = <0>;25 compatible = "arm,cortex-a53", "arm,armv8";27 enable-method = "psci";28 operating-points-v2 = <&cpu_opp_table>;30 cpu-idle-states = <&CPU_SLEEP_0>;[all …]
1 # SPDX-License-Identifier: GPL-2.03 bool "Xilinx Zynq ARM Cortex A9 Platform"13 select PINCTRL17 Support for Xilinx Zynq ARM Cortex A9 Platform
1 # SPDX-License-Identifier: GPL-2.0-only3 # PINCTRL infrastructure and drivers6 menuconfig PINCTRL config9 if PINCTRL29 bool "Debug PINCTRL calls"32 Say Y here to add some extra checks and diagnostics to PINCTRL calls.66 will be called pinctrl-apple-gpio.69 bool "Axis ARTPEC-6 pin controller driver"74 This is the driver for the Axis ARTPEC-6 pin controller. This driver77 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt[all …]
1 # SPDX-License-Identifier: GPL-2.04 subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG6 obj-y += core.o pinctrl-utils.o7 obj-$(CONFIG_PINMUX) += pinmux.o8 obj-$(CONFIG_PINCONF) += pinconf.o9 obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o10 obj-$(CONFIG_OF) += devicetree.o12 obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o13 obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o14 obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Zynq pin controller15 #include <linux/pinctrl/pinctrl.h>16 #include <linux/pinctrl/pinmux.h>17 #include <linux/pinctrl/pinconf.h>18 #include <linux/pinctrl/pinconf-generic.h>20 #include "pinctrl-utils.h"32 * struct zynq_pinctrl - driver data33 * @pctrl: Pinctrl device35 * @pctrl_offset: Offset for pinctrl into the @syscon space[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Xu Yang <xu.yang_2@nxp.com>11 - Peng Fan <peng.fan@nxp.com>16 - enum:17 - chipidea,usb218 - lsi,zevio-usb19 - nuvoton,npcm750-udc[all …]
8 W: Web-page with status/info24 N: [^a-z]tegra all files whose path contains the word tegra52 -----------------------------------57 L: uboot-snps-arc@synopsys.com58 T: git git://git.denx.de/u-boot-arc.git65 L: uboot-snps-arc@synopsys.com66 F: drivers/clk/clk-hsdk-cgu.c67 F: include/dt-bindings/clock/snps,hsdk-cgu.h68 F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt73 L: uboot-snps-arc@synopsys.com[all …]
15 is defined in include/asm-generic/gpio.h.24 is a mechanism providing automatic GPIO request and config-25 uration as part of the gpio-controller's driver probe function.34 is a mechanism providing automatic GPIO request and config-35 uration as part of the gpio-controller's driver probe function.64 lines. Each I/O line may be dedicated as a general-purpose67 the responsibility of AT91 Pinctrl driver. This driver is68 responsible for the general-purpose I/O.149 - APQ8016150 - MSM8916[all …]
14 bool "Generate position-independent pre-relocation code"16 U-Boot expects to be linked to a specific hard-coded address, and to20 information that is embedded into the binary to support U-Boot21 relocating itself to the top-of-RAM later during execution.28 U-Boot typically uses a hard-coded value for the stack pointer30 initial SP at run-time. This is useful to avoid hard-coding addresses31 into U-Boot, so that can be loaded and executed at arbitrary41 Place a Linux kernel image header at the start of the U-Boot binary.45 U-Boot needs to use, but which isn't part of the binary.74 Do not enable instruction cache in U-Boot[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2014 - 2021, Xilinx, Inc.15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/interrupt-controller/arm-gic.h>18 #include <dt-bindings/interrupt-controller/irq.h>19 #include <dt-bindings/power/xlnx-zynqmp-power.h>20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>24 #address-cells = <2>;25 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later5 * Copyright (C) 2009 - 2014 Xilinx, Inc.18 #include <linux/pinctrl/consumer.h>121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3)123 #define DRIVER_NAME "cdns-i2c"134 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)135 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)139 * enum cdns_i2c_mode - I2C Controller current operating mode150 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode164 * struct cdns_i2c - I2C device private data structure[all …]
1 # SPDX-License-Identifier: GPL-2.0-only47 this symbol, but new drivers should use the generic gpio-regmap57 non-sleeping contexts. They can make bitbanged serial protocols118 Enables support for the idio-16 library functions. The idio-16 library120 ACCES IDIO-16 family such as the 104-IDIO-16 and the PCI-IDIO-16.122 If built as a module its name will be gpio-idio-16.128 tristate "GPIO driver for 74xx-ICs with MMIO access"132 Say yes here to support GPIO functionality for 74xx-compatible ICs149 If driver is built as a module it will be called gpio-altera.310 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]
1 # SPDX-License-Identifier: GPL-2.0-only44 This clock should be battery-backed, so that it reads the correct45 time when the system boots from a power-off state. Otherwise, your141 once-per-second update interrupts, used for synchronization.159 will be called rtc-test.173 will be called rtc-88pm860x.183 will be called rtc-88pm80x.187 tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3"190 AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip.193 will be called rtc-ab-b5ze-s3.[all …]
1 # SPDX-License-Identifier: GPL-2.0150 The ARM series is a line of low-power-consumption RISC chip designs152 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer153 manufactured, but legacy ARM-based PC hardware remains popular in164 supported in LLD until version 14. The combined range is -/+ 256 MiB,257 Patch phys-to-virt and virt-to-phys translation functions at261 This can only be used with non-XIP MMU kernels where the base307 bool "MMU-based Paged Memory Management Support"310 Select if you want MMU-based virtualised addressing space350 # https://github.com/llvm/llvm-project/issues/50764[all …]
... --------------------- ...