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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,fimd.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,s3c2443-fimd
19 - samsung,s3c6400-fimd
20 - samsung,s5pv210-fimd
[all …]
H A Dsamsung,exynos7-decon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
22 const: samsung,exynos7-decon
27 clock-names:
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-crs328-4c-20s-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS328-4C-20S-4S+ board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS328-4C-20S-4S+";
25 compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
38 arm,parity-enable;
39 marvell,ecc-enable;
[all …]
H A Darmada-xp-crs305-1g-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS305-1G-4S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS305-1G-4S+";
25 compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
38 arm,parity-enable;
39 marvell,ecc-enable;
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H A Darmada-xp-crs326-24g-2s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS326-24G-2S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS326-24G-2S+";
25 compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
38 arm,parity-enable;
39 marvell,ecc-enable;
[all …]
H A Darmada-xp-db-xc3-24g4xg.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-XC3-24G4XG board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx3336.dtsi"
23 model = "DB-XC3-24G4XG";
24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
37 arm,parity-enable;
38 marvell,ecc-enable;
[all …]
H A Darmada-xp-db-dxbc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-DXBC2 board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx4251.dtsi"
24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
43 devbus,bus-width = <16>;
44 devbus,turn-off-ps = <60000>;
45 devbus,badr-skew-ps = <0>;
[all …]
H A Darmada-xp-openblocks-ax3-4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for OpenBlocks AX3-4 board
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "armada-xp-mv78260.dtsi"
16 model = "PlatHome OpenBlocks AX3-4 board";
17 …compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell…
20 stdout-path = "serial0:115200n8";
[all …]
H A Darmada-385-atl-x530.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 (x530/AT-GS980MX)
9 /dts-v1/;
10 #include "armada-385.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
15 model = "x530/AT-GS980MX";
19 stdout-path = "serial1:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
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H A Darmada-xp-gp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-xp-mv78460.dtsi"
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
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H A Darmada-xp-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-78460-BP)
6 * Copyright (C) 2012-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
23 /dts-v1/;
24 #include "armada-xp-mv78460.dtsi"
28 …compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
31 stdout-path = "serial0:115200n8";
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfbtft-io.c1 // SPDX-License-Identifier: GPL-2.0
16 fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len, in fbtft_write_spi()
19 if (!par->spi) { in fbtft_write_spi()
20 dev_err(par->info->device, in fbtft_write_spi()
21 "%s: par->spi is unexpectedly NULL\n", __func__); in fbtft_write_spi()
22 return -1; in fbtft_write_spi()
27 return spi_sync(par->spi, &m); in fbtft_write_spi()
32 * fbtft_write_spi_emulate_9() - write SPI emulating 9-bit
37 * When 9-bit SPI is not available, this function can be used to emulate that.
38 * par->extra must hold a transformation buffer used for transfer.
[all …]
/openbmc/linux/arch/mips/include/uapi/asm/
H A Ducontext.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
6 * struct extcontext - extended context header structure
26 * struct msa_extcontext - MSA extended context structure
28 * @wr: the most significant 64 bits of each MSA vector register
32 * this structure will hold the MSA context of the task as it was prior to the
39 unsigned long long wr[32]; member
46 * struct ucontext - user context structure
55 /* Historic fields matching asm-generic */
/openbmc/linux/include/linux/platform_data/
H A Dvideo-pxafb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Author: Jean-Frederic Clere
15 * bits 0 - 3: for LCD panel type:
17 * STN - for passive matrix
18 * DSTN - for dual scan passive matrix
19 * TFT - for active matrix
21 * bits 4 - 9 : for bus width
22 * bits 10-17 : for AC Bias Pin Frequency
61 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
86 /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
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H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
82 * ideally for adv_rd/(wr)_off it should have considered
89 u32 t_aavdh; /* address hold time */
108 u32 t_avdh; /* ADV hold time from clk */
109 u32 t_ach; /* address hold time from clk */
118 u8 cyc_aavdh_oe;/* read address hold time in cycles */
119 u8 cyc_aavdh_we;/* write address hold time in cycles */
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Drtrap_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
31 * the ADI security, we must re-enable PSTATE.mcde before
47 * the ADI security, we must re-enable PSTATE.mcde before
73 * the ADI security, we must re-enable PSTATE.mcde before
105 * If we re-enable interrupts here, we can recurse down
128 * If we re-enable interrupts here, we can recurse down
143 /* We must hold IRQs off and atomically test schedule+signal
144 * state, then hold them off all the way back to userspace.
179 /* This fpdepth clear is necessary for non-syscall rtraps only */
224 wr %o3, %g0, %y
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt5 compatible: should be "samsung,exynos-fimd"
9 samsung,vl-col: X resolution of the panel
10 samsung,vl-row: Y resolution of the panel
11 samsung,vl-freq: Refresh rate
12 samsung,vl-bpix: Bits per pixel
13 samsung,vl-hspw: Hsync value
14 samsung,vl-hfpd: Right margin
15 samsung,vl-hbpd: Left margin
16 samsung,vl-vspw: Vsync value
17 samsung,vl-vfpd: Lower margin
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/mei/
H A Dmain.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2021-2023 Intel Corporation
23 #include "iwl-mei.h"
25 #include "trace-data.h"
40 * Since iwlwifi calls iwlmei without any context, hold a pointer to the
96 * +-----------------------------------+
98 * +-----------------------------------+
99 * |Host -> ME data queue |
100 * +-----------------------------------+
101 * |Host -> ME notif queue |
[all …]
/openbmc/linux/include/rdma/
H A Drdmavt_qp.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright(c) 2016 - 2020 Intel Corporation.
13 #include <rdma/rvt-abi.h>
54 #define RVT_AIP_QP_MAX (u32)(RVT_AIP_QP_BASE + RVT_AIP_QPN_MAX - 1)
59 * RVT_S_SIGNAL_REQ_WR - set if QP send WRs contain completion signaled
60 * RVT_S_BUSY - send tasklet is processing the QP
61 * RVT_S_TIMER - the RC retry timer is active
62 * RVT_S_ACK_PENDING - an ACK is waiting to be sent after RDMA read/atomics
63 * RVT_S_WAIT_FENCE - waiting for all prior RDMA read or atomic SWQEs
65 * RVT_S_WAIT_RDMAR - waiting for a RDMA read or atomic SWQE to complete
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-385-atl-x530.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/gpio.h>
4 #include "armada-385.dtsi"
11 stdout-path = "serial0:115200n8";
30 pcie-mem-aperture = <0xa0000000 0x40000000>;
33 eco-button-interrupt {
34 compatible = "atl,eco-button-interrupt";
35 eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
38 board-reset {
40 /* Physical board layout of reset pin is active-low but for the
[all …]
H A Darmada-xp-maxbcm.dts4 * Copyright (C) 2013-2014 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
51 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
58 /dts-v1/;
59 #include <dt-bindings/gpio/gpio.h>
60 #include "armada-xp-mv78460.dtsi"
64 …compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
67 stdout-path = "serial0:115200n8";
[all …]
/openbmc/linux/arch/mips/mm/
H A Dtlbex.c10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
34 #include <asm/cpu-type.h>
131 * CVMSEG starts at address -32768 and extends for in scratchpad_offset()
135 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset()
262 unsigned int count = (end - start) / sizeof(u32); in dump_handler()
307 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
338 return -1; in allocate_kscratch()
340 r--; /* make it zero based */ in allocate_kscratch()
438 (unsigned int)(p - tlb_handler)); in build_r3000_tlb_refill_handler()
470 * The software work-around is to not allow the instruction preceding the TLBP
[all …]
/openbmc/linux/net/sunrpc/xprtrdma/
H A Dfrwr_ops.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2003-2007 Network Appliance, Inc. All rights reserved.
11 * of arbitrarily-sized memory regions. This is the fastest and safest
32 * send lock, just as ->send_request does. This prevents frwr_map and
51 struct rpc_rdma_cid *cid = &mr->mr_cid; in frwr_cid_init()
53 cid->ci_queue_id = ep->re_attr.send_cq->res.id; in frwr_cid_init()
54 cid->ci_completion_id = mr->mr_ibmr->res.id; in frwr_cid_init()
59 if (mr->mr_device) { in frwr_mr_unmap()
61 ib_dma_unmap_sg(mr->mr_device, mr->mr_sg, mr->mr_nents, in frwr_mr_unmap()
62 mr->mr_dir); in frwr_mr_unmap()
[all …]
/openbmc/linux/sound/pci/asihpi/
H A Dhpi6000.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com>
18 (C) Copyright AudioScience Inc. 1998-2003
78 /* can't access SDRAM - test#1 */
80 /* can't access SDRAM - test#2 */
210 switch (phm->function) { in subsys_message()
215 phr->error = HPI_ERROR_INVALID_FUNC; in subsys_message()
223 struct hpi_hw_obj *phw = pao->priv; in control_message()
225 switch (phm->function) { in control_message()
227 if (pao->has_control_cache) { in control_message()
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