1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2293b2da1SArnd Bergmann /*
3293b2da1SArnd Bergmann * Support for the xscale frame buffer.
4293b2da1SArnd Bergmann *
5293b2da1SArnd Bergmann * Author: Jean-Frederic Clere
6293b2da1SArnd Bergmann * Created: Sep 22, 2003
7293b2da1SArnd Bergmann * Copyright: jfclere@sinix.net
8293b2da1SArnd Bergmann */
9293b2da1SArnd Bergmann
10293b2da1SArnd Bergmann #include <linux/fb.h>
11293b2da1SArnd Bergmann
12293b2da1SArnd Bergmann /*
13293b2da1SArnd Bergmann * Supported LCD connections
14293b2da1SArnd Bergmann *
15293b2da1SArnd Bergmann * bits 0 - 3: for LCD panel type:
16293b2da1SArnd Bergmann *
17293b2da1SArnd Bergmann * STN - for passive matrix
18293b2da1SArnd Bergmann * DSTN - for dual scan passive matrix
19293b2da1SArnd Bergmann * TFT - for active matrix
20293b2da1SArnd Bergmann *
21293b2da1SArnd Bergmann * bits 4 - 9 : for bus width
22293b2da1SArnd Bergmann * bits 10-17 : for AC Bias Pin Frequency
23293b2da1SArnd Bergmann * bit 18 : for output enable polarity
24293b2da1SArnd Bergmann * bit 19 : for pixel clock edge
25293b2da1SArnd Bergmann * bit 20 : for output pixel format when base is RGBT16
26293b2da1SArnd Bergmann */
27293b2da1SArnd Bergmann #define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
28293b2da1SArnd Bergmann #define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
29293b2da1SArnd Bergmann
30293b2da1SArnd Bergmann #define LCD_TYPE_MASK 0xf
31293b2da1SArnd Bergmann #define LCD_TYPE_UNKNOWN 0
32293b2da1SArnd Bergmann #define LCD_TYPE_MONO_STN 1
33293b2da1SArnd Bergmann #define LCD_TYPE_MONO_DSTN 2
34293b2da1SArnd Bergmann #define LCD_TYPE_COLOR_STN 3
35293b2da1SArnd Bergmann #define LCD_TYPE_COLOR_DSTN 4
36293b2da1SArnd Bergmann #define LCD_TYPE_COLOR_TFT 5
37293b2da1SArnd Bergmann #define LCD_TYPE_SMART_PANEL 6
38293b2da1SArnd Bergmann #define LCD_TYPE_MAX 7
39293b2da1SArnd Bergmann
40293b2da1SArnd Bergmann #define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
41293b2da1SArnd Bergmann #define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
42293b2da1SArnd Bergmann #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
43293b2da1SArnd Bergmann #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
44293b2da1SArnd Bergmann #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
45293b2da1SArnd Bergmann #define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT)
46293b2da1SArnd Bergmann #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
47293b2da1SArnd Bergmann #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
48293b2da1SArnd Bergmann #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
49293b2da1SArnd Bergmann #define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
50293b2da1SArnd Bergmann #define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
51293b2da1SArnd Bergmann
52293b2da1SArnd Bergmann #define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
53293b2da1SArnd Bergmann #define LCD_BIAS_ACTIVE_HIGH (0 << 18)
54293b2da1SArnd Bergmann #define LCD_BIAS_ACTIVE_LOW (1 << 18)
55293b2da1SArnd Bergmann #define LCD_PCLK_EDGE_RISE (0 << 19)
56293b2da1SArnd Bergmann #define LCD_PCLK_EDGE_FALL (1 << 19)
57293b2da1SArnd Bergmann #define LCD_ALTERNATE_MAPPING (1 << 20)
58293b2da1SArnd Bergmann
59293b2da1SArnd Bergmann /*
60293b2da1SArnd Bergmann * This structure describes the machine which we are running on.
61293b2da1SArnd Bergmann * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
62293b2da1SArnd Bergmann * of linux/drivers/video/pxafb.c
63293b2da1SArnd Bergmann */
64293b2da1SArnd Bergmann struct pxafb_mode_info {
65293b2da1SArnd Bergmann u_long pixclock;
66293b2da1SArnd Bergmann
67293b2da1SArnd Bergmann u_short xres;
68293b2da1SArnd Bergmann u_short yres;
69293b2da1SArnd Bergmann
70293b2da1SArnd Bergmann u_char bpp;
71293b2da1SArnd Bergmann u_int cmap_greyscale:1,
72293b2da1SArnd Bergmann depth:8,
73293b2da1SArnd Bergmann transparency:1,
74293b2da1SArnd Bergmann unused:22;
75293b2da1SArnd Bergmann
76293b2da1SArnd Bergmann /* Parallel Mode Timing */
77293b2da1SArnd Bergmann u_char hsync_len;
78293b2da1SArnd Bergmann u_char left_margin;
79293b2da1SArnd Bergmann u_char right_margin;
80293b2da1SArnd Bergmann
81293b2da1SArnd Bergmann u_char vsync_len;
82293b2da1SArnd Bergmann u_char upper_margin;
83293b2da1SArnd Bergmann u_char lower_margin;
84293b2da1SArnd Bergmann u_char sync;
85293b2da1SArnd Bergmann
86293b2da1SArnd Bergmann /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
87293b2da1SArnd Bergmann * Note:
88293b2da1SArnd Bergmann * 1. all parameters in nanosecond (ns)
89293b2da1SArnd Bergmann * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
90293b2da1SArnd Bergmann * in pxa27x and pxa3xx, initialize them to the same value or
91293b2da1SArnd Bergmann * the larger one will be used
92293b2da1SArnd Bergmann * 3. same to {rd,wr}_pulse_width
93293b2da1SArnd Bergmann *
94293b2da1SArnd Bergmann * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
95293b2da1SArnd Bergmann * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
96293b2da1SArnd Bergmann * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
97293b2da1SArnd Bergmann */
98293b2da1SArnd Bergmann unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
99293b2da1SArnd Bergmann unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
100293b2da1SArnd Bergmann unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
101293b2da1SArnd Bergmann unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
102293b2da1SArnd Bergmann unsigned cmd_inh_time; /* Command Inhibit time between two writes */
103293b2da1SArnd Bergmann unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
104293b2da1SArnd Bergmann };
105293b2da1SArnd Bergmann
106293b2da1SArnd Bergmann struct pxafb_mach_info {
107293b2da1SArnd Bergmann struct pxafb_mode_info *modes;
108293b2da1SArnd Bergmann unsigned int num_modes;
109293b2da1SArnd Bergmann
110293b2da1SArnd Bergmann unsigned int lcd_conn;
111293b2da1SArnd Bergmann unsigned long video_mem_size;
112293b2da1SArnd Bergmann
113293b2da1SArnd Bergmann u_int fixed_modes:1,
114293b2da1SArnd Bergmann cmap_inverse:1,
115293b2da1SArnd Bergmann cmap_static:1,
116293b2da1SArnd Bergmann acceleration_enabled:1,
117293b2da1SArnd Bergmann unused:28;
118293b2da1SArnd Bergmann
119293b2da1SArnd Bergmann /* The following should be defined in LCCR0
120293b2da1SArnd Bergmann * LCCR0_Act or LCCR0_Pas Active or Passive
121293b2da1SArnd Bergmann * LCCR0_Sngl or LCCR0_Dual Single/Dual panel
122293b2da1SArnd Bergmann * LCCR0_Mono or LCCR0_Color Mono/Color
123293b2da1SArnd Bergmann * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
124293b2da1SArnd Bergmann * LCCR0_DMADel(Tcpu) (optional) DMA request delay
125293b2da1SArnd Bergmann *
126293b2da1SArnd Bergmann * The following should not be defined in LCCR0:
127293b2da1SArnd Bergmann * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
128293b2da1SArnd Bergmann * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
129293b2da1SArnd Bergmann */
130293b2da1SArnd Bergmann u_int lccr0;
131293b2da1SArnd Bergmann /* The following should be defined in LCCR3
132293b2da1SArnd Bergmann * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
133293b2da1SArnd Bergmann * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
134293b2da1SArnd Bergmann * LCCR3_Acb(X) AB Bias pin frequency
135293b2da1SArnd Bergmann * LCCR3_DPC (optional) Double Pixel Clock mode (untested)
136293b2da1SArnd Bergmann *
137293b2da1SArnd Bergmann * The following should not be defined in LCCR3
138293b2da1SArnd Bergmann * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
139293b2da1SArnd Bergmann */
140293b2da1SArnd Bergmann u_int lccr3;
141293b2da1SArnd Bergmann /* The following should be defined in LCCR4
142293b2da1SArnd Bergmann * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
143293b2da1SArnd Bergmann *
144293b2da1SArnd Bergmann * All other bits in LCCR4 should be left alone.
145293b2da1SArnd Bergmann */
146293b2da1SArnd Bergmann u_int lccr4;
147293b2da1SArnd Bergmann void (*pxafb_backlight_power)(int);
148293b2da1SArnd Bergmann void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
149293b2da1SArnd Bergmann void (*smart_update)(struct fb_info *);
150293b2da1SArnd Bergmann };
151293b2da1SArnd Bergmann
152293b2da1SArnd Bergmann void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
153293b2da1SArnd Bergmann unsigned long pxafb_get_hsync_time(struct device *dev);
154293b2da1SArnd Bergmann
155*ee84cbd5SArnd Bergmann /* smartpanel related */
156*ee84cbd5SArnd Bergmann #define SMART_CMD_A0 (0x1 << 8)
157*ee84cbd5SArnd Bergmann #define SMART_CMD_READ_STATUS_REG (0x0 << 9)
158*ee84cbd5SArnd Bergmann #define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0)
159*ee84cbd5SArnd Bergmann #define SMART_CMD_WRITE_COMMAND (0x1 << 9)
160*ee84cbd5SArnd Bergmann #define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0)
161*ee84cbd5SArnd Bergmann #define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0)
162*ee84cbd5SArnd Bergmann #define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9)
163*ee84cbd5SArnd Bergmann #define SMART_CMD_NOOP (0x4 << 9)
164*ee84cbd5SArnd Bergmann #define SMART_CMD_INTERRUPT (0x5 << 9)
165*ee84cbd5SArnd Bergmann
166*ee84cbd5SArnd Bergmann #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
167*ee84cbd5SArnd Bergmann #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff))
168*ee84cbd5SArnd Bergmann
169*ee84cbd5SArnd Bergmann /* SMART_DELAY() is introduced for software controlled delay primitive which
170*ee84cbd5SArnd Bergmann * can be inserted between command sequences, unused command 0x6 is used here
171*ee84cbd5SArnd Bergmann * and delay ranges from 0ms ~ 255ms
172*ee84cbd5SArnd Bergmann */
173*ee84cbd5SArnd Bergmann #define SMART_CMD_DELAY (0x6 << 9)
174*ee84cbd5SArnd Bergmann #define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff))
175*ee84cbd5SArnd Bergmann
176293b2da1SArnd Bergmann #ifdef CONFIG_FB_PXA_SMARTPANEL
177293b2da1SArnd Bergmann extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
178293b2da1SArnd Bergmann extern int pxafb_smart_flush(struct fb_info *info);
179293b2da1SArnd Bergmann #else
pxafb_smart_queue(struct fb_info * info,uint16_t * cmds,int n)180293b2da1SArnd Bergmann static inline int pxafb_smart_queue(struct fb_info *info,
181293b2da1SArnd Bergmann uint16_t *cmds, int n)
182293b2da1SArnd Bergmann {
183293b2da1SArnd Bergmann return 0;
184293b2da1SArnd Bergmann }
185293b2da1SArnd Bergmann
pxafb_smart_flush(struct fb_info * info)186293b2da1SArnd Bergmann static inline int pxafb_smart_flush(struct fb_info *info)
187293b2da1SArnd Bergmann {
188293b2da1SArnd Bergmann return 0;
189293b2da1SArnd Bergmann }
190293b2da1SArnd Bergmann #endif
191