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Searched +full:wdt +full:- +full:r1p2 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dcdns,wdt-r1p2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
19 - $ref: watchdog.yaml#
24 - cdns,wdt-r1p2
35 reset-on-timeout:
42 - compatible
43 - reg
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/openbmc/u-boot/drivers/watchdog/
H A Dcdns_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence WDT driver - Used by Xilinx Zynq
11 #include <wdt.h>
18 u32 zmr; /* WD Zero mode register, offset - 0x0 */
19 u32 ccr; /* Counter Control Register offset - 0x4 */
20 u32 restart; /* Restart key register, offset - 0x8 */
21 u32 status; /* Status Register, offset - 0xC */
32 /* Supports 1 - 516 sec */
62 * Zero Mode Register - This register controls how the time out is indicated
65 #define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
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/openbmc/linux/drivers/watchdog/
H A Dcadence_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
21 /* Supports 1 - 516 sec */
63 * struct cdns_wdt - Watchdog device structure
85 static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val) in cdns_wdt_writereg() argument
87 writel_relaxed(val, wdt->regs + offset); in cdns_wdt_writereg()
92 /* Register Offsets for the WDT */
99 * Zero Mode Register - This register controls how the time out is indicated
102 #define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
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/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
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H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/openbmc/linux/
H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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