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/openbmc/linux/arch/mips/mm/
H A Dc-octeon.c184 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
188 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
194 c->dcache.ways = 64; in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
197 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; in probe_octeon()
204 c->icache.ways = 37; in probe_octeon()
206 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
209 c->dcache.ways = 32; in probe_octeon()
211 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
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H A Dc-r4k.c233 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32()
1010 c->icache.ways = 2; in probe_pcache()
1015 c->dcache.ways = 2; in probe_pcache()
1024 c->icache.ways = 2; in probe_pcache()
1029 c->dcache.ways = 2; in probe_pcache()
1038 c->icache.ways = 4; in probe_pcache()
1043 c->dcache.ways = 4; in probe_pcache()
1059 c->icache.ways = 1; in probe_pcache()
1064 c->dcache.ways = 1; in probe_pcache()
1076 c->icache.ways = 2; in probe_pcache()
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H A Dsc-mips.c170 c->scache.ways = assoc + 1; in mips_sc_probe_cm3()
220 c->scache.ways = tmp + 1; in mips_sc_probe()
227 * According to config2 it would be 5-ways, but that is in mips_sc_probe()
232 c->scache.ways = 4; in mips_sc_probe()
236 * According to config2 it would be 5-ways and 512-sets, in mips_sc_probe()
242 c->scache.ways = 4; in mips_sc_probe()
H A Dsc-rm7k.c238 c->scache.ways = 4; in rm7k_sc_init()
239 c->scache.waybit= __ffs(scache_size / c->scache.ways); in rm7k_sc_init()
240 c->scache.waysize = scache_size / c->scache.ways; in rm7k_sc_init()
241 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in rm7k_sc_init()
268 c->tcache.ways = 1; in rm7k_sc_init()
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dcache-uniphier.c91 * @ways: target ways (don't care for operations other than pre-fetch, touch
94 static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways, in uniphier_cache_maint_common() argument
110 /* set target ways if needed */ in uniphier_cache_maint_common()
112 writel(ways, UNIPHIER_SSCOQWN); in uniphier_cache_maint_common()
128 static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways, in uniphier_cache_maint_range() argument
156 uniphier_cache_maint_common(start, chunk_size, ways, in uniphier_cache_maint_range()
166 void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways) in uniphier_cache_prefetch_range() argument
168 uniphier_cache_maint_range(start, end, ways, in uniphier_cache_prefetch_range()
173 void uniphier_cache_touch_range(u32 start, u32 end, u32 ways) in uniphier_cache_touch_range() argument
175 uniphier_cache_maint_range(start, end, ways, in uniphier_cache_touch_range()
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H A Dcache-uniphier.h12 void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways);
13 void uniphier_cache_touch_range(u32 start, u32 end, u32 ways);
14 void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways);
15 void uniphier_cache_inv_way(u32 ways);
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dprobe.c38 boot_cpu_data.icache.ways = 1; in cpu_probe()
47 boot_cpu_data.dcache.ways = 1; in cpu_probe()
67 boot_cpu_data.icache.ways = 4; in cpu_probe()
68 boot_cpu_data.dcache.ways = 4; in cpu_probe()
171 boot_cpu_data.icache.ways = 2; in cpu_probe()
172 boot_cpu_data.dcache.ways = 2; in cpu_probe()
176 boot_cpu_data.icache.ways = 2; in cpu_probe()
177 boot_cpu_data.dcache.ways = 2; in cpu_probe()
192 boot_cpu_data.icache.ways = 2; in cpu_probe()
193 boot_cpu_data.dcache.ways = 2; in cpu_probe()
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/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h134 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
141 * set = group of contiguous ways with exactly identical parameters
143 * from the page table and storing it in one of the auto-refill ways;
153 * TLB ways that support multiple page sizes:
159 * this list may be sparse for auto-refill ways because auto-refill
160 * ways have independent lists of supported page sizes sharing a
164 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
177 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
178 #define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
179 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
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/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h150 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
157 * set = group of contiguous ways with exactly identical parameters
159 * from the page table and storing it in one of the auto-refill ways;
169 * TLB ways that support multiple page sizes:
175 * this list may be sparse for auto-refill ways because auto-refill
176 * ways have independent lists of supported page sizes sharing a
180 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
193 #define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
194 #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
195 #define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Dcache.json54 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
57 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
60 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
63 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
66 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
69 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
H A Dbcm2836.dtsi58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
118 cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
/openbmc/linux/arch/sh/mm/
H A Dcache-sh7705.c33 unsigned long ways, waysize, addrstart; in cache_wback_all() local
35 ways = current_cpu_data.dcache.ways; in cache_wback_all()
58 } while (--ways); in cache_wback_all()
82 unsigned long ways, waysize, addrstart; in __flush_dcache_page() local
103 ways = current_cpu_data.dcache.ways; in __flush_dcache_page()
125 } while (--ways); in __flush_dcache_page()
H A Dtlb-sh3.c58 int i, ways = MMU_NTLB_WAYS; in local_flush_tlb_one() local
71 ways = 1; /* we already know the way .. */ in local_flush_tlb_one()
74 for (i = 0; i < ways; i++) in local_flush_tlb_one()
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dcache.json111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
123 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
126 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h188 * the cache 'ways' that a core can evict from.
197 * @mask: The partitioning of the ways expressed as a binary
204 * @note If any ways are blocked for all cores and the HW blocks, then
205 * those ways will never have any cache lines evicted from them.
207 * ways regardless of the partitioning.
215 * the cache 'ways' that a core can evict from.
223 * @mask: The partitioning of the ways expressed as a binary
230 * @note If any ways are blocked for all cores and the HW blocks, then
231 * those ways will never have any cache lines evicted from them.
233 * ways regardless of the partitioning.
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/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c49 INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
52 FLUSH_SET_WAY, /* d-cache clean by sets/ways */
54 FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
59 u32 ways; member
67 cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; in get_cache_ways_sets()
73 * & invalidate by sets/ways.
184 get_cache_ways_sets(&cache); /* Get number of ways & sets */ in action_dcache_all()
185 debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1); in action_dcache_all()
187 for (j = cache.ways; j >= 0; j--) { in action_dcache_all()
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_npc_hash.c474 /* Check all the 4 ways for a free slot. */ in rvu_npc_exact_alloc_mem_table_entry()
476 for (i = 0; i < table->mem_table.ways; i++) { in rvu_npc_exact_alloc_mem_table_entry()
771 * @ways: MEM table ways.
784 static int rvu_npc_exact_add_to_list(struct rvu *rvu, enum npc_exact_opc_type opc_type, u8 ways, in rvu_npc_exact_add_to_list() argument
792 WARN_ON(ways >= NPC_EXACT_TBL_MAX_WAYS); in rvu_npc_exact_add_to_list()
814 lhead = &table->lhead_mem_tbl_entry[ways]; in rvu_npc_exact_add_to_list()
832 entry->ways = ways; in rvu_npc_exact_add_to_list()
868 * @ways: ways for MEM table.
872 static void rvu_npc_exact_mem_table_write(struct rvu *rvu, int blkaddr, u8 ways, in rvu_npc_exact_mem_table_write() argument
875 rvu_write64(rvu, blkaddr, NPC_AF_EXACT_MEM_ENTRY(ways, index), mdata); in rvu_npc_exact_mem_table_write()
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/openbmc/linux/arch/sh/kernel/cpu/
H A Dinit.c126 unsigned long ways, waysize, addrstart; in cache_init() local
144 ways = 1; in cache_init()
147 ways = current_cpu_data.dcache.ways; in cache_init()
159 } while (--ways); in cache_init()
170 if (current_cpu_data.dcache.ways > 1) in cache_init()
200 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
/openbmc/linux/arch/arc/mm/
H A Dtlb.c22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; member
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
585 mmu->ways = 1 << mmu3->ways; in arc_mmu_mumbojumbo()
594 mmu->ways = mmu4->n_ways * 2; in arc_mmu_mumbojumbo()
609 mmu->sets, mmu->ways, in arc_mmu_mumbojumbo()
686 * However for walking WAYS of a SET, we need to know this
688 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
693 * time of lookup matching multiple ways.
705 int set, n_ways = mmu->ways; in do_tlb_overlap_fault()
708 BUG_ON(mmu->ways > 4); in do_tlb_overlap_fault()
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/openbmc/linux/drivers/cxl/
H A Dacpi.c145 unsigned int ways; in cxl_acpi_cfmws_verify() local
164 rc = eiw_to_ways(cfmws->interleave_ways, &ways); in cxl_acpi_cfmws_verify()
166 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n", in cxl_acpi_cfmws_verify()
171 expected_len = struct_size(cfmws, interleave_targets, ways); in cxl_acpi_cfmws_verify()
208 unsigned int ways, i, ig; in __cxl_parse_cfmws() local
220 rc = eiw_to_ways(cfmws->interleave_ways, &ways); in __cxl_parse_cfmws()
226 for (i = 0; i < ways; i++) in __cxl_parse_cfmws()
251 cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb); in __cxl_parse_cfmws()
262 cxld->interleave_ways = ways; in __cxl_parse_cfmws()
267 if (ways == 1) in __cxl_parse_cfmws()
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H A Dcxl.h88 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) in eiw_to_ways() argument
92 *ways = 1 << eiw; in eiw_to_ways()
95 *ways = 3 << (eiw - 8); in eiw_to_ways()
113 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) in ways_to_eiw() argument
115 if (ways > 16) in ways_to_eiw()
117 if (is_power_of_2(ways)) { in ways_to_eiw()
118 *eiw = ilog2(ways); in ways_to_eiw()
121 if (ways % 3) in ways_to_eiw()
123 ways /= 3; in ways_to_eiw()
124 if (!is_power_of_2(ways)) in ways_to_eiw()
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/openbmc/linux/Documentation/devicetree/bindings/nios2/
H A Dnios2.txt23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
52 altr,tlb-num-ways = <16>;
/openbmc/linux/arch/arm/include/asm/
H A Dshmparam.h6 * This should be the size of the virtually indexed cache/ways,
8 * every size/ways bytes.
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dcache.S33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
34 clz w5, w3 /* bit position of #ways */
39 /* x3 <- number of cache ways - 1 */
41 /* x5 <- bit position of #ways */
44 mov x6, x3 /* x6 <- working copy of #ways */

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