Home
last modified time | relevance | path

Searched +full:watchdog +full:- +full:timers (Results 1 – 25 of 201) sorted by relevance

123456789

/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
11 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
18 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
25 ti,timers = <&timer3>;
26 ti,watchdog-timers = <&timer4>, <&timer9>;
31 ti,timers = <&timer11>;
32 ti,watchdog-timers = <&timer7>, <&timer8>;
37 ti,timers = <&timer5>;
38 ti,watchdog-timers = <&timer10>;
H A Ddra74-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "dra7-ipu-dsp-common.dtsi"
9 mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
16 ti,timers = <&timer6>;
17 ti,watchdog-timers = <&timer13>;
H A Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
/openbmc/linux/drivers/remoteproc/
H A Domap_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * Ohad Ben-Cohen <ohad@wizery.com>
12 * Suman Anna <s-anna@ti.com>
13 * Hari Kanigeri <h-kanigeri2@ti.com>
27 #include <linux/dma-mapping.h>
31 #include <linux/omap-iommu.h>
32 #include <linux/omap-mailbox.h>
36 #include <clocksource/timer-ti-dm.h>
38 #include <linux/platform_data/dmtimer-omap.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dti,davinci-timer.txt3 This document provides bindings for the 64-bit timer in the DaVinci
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
6 timers, each half can operate in conjunction (chain mode) or independently
9 The timer is a free running up-counter and can generate interrupts when the
12 Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
13 watchdog timers.
17 - compatible : should be "ti,da830-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupts generated by the timer.
[all …]
/openbmc/qemu/include/hw/timer/
H A Dnpcm7xx_timer.h23 /* Each Timer Module (TIM) instance holds five 25 MHz timers. */
32 /* The basic watchdog timer period is 2^14 clock cycles. */
35 #define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
40 * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
41 * watchdog timer use.
53 * struct NPCM7xxTimer - Individual timer state.
71 * struct NPCM7xxWatchdogTimer - The watchdog timer state.
76 * @wtcr: The Watchdog Timer Control Register.
89 * struct NPCM7xxTimerCtrlState - Timer Module device state.
94 * @timer: The five individual timers managed by this module.
[all …]
/openbmc/linux/drivers/watchdog/
H A Di6300esb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
8 * based on i810-tco.c which is in turn based on softdog.c
12 * 6300ESB chip : document number 300641-004
21 * Change driver to use the watchdog subsystem
35 #include <linux/watchdog.h>
49 #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
50 #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
51 #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
52 #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
[all …]
H A Dsp805_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/char/watchdog/sp805-wdt.c
5 * Watchdog driver for ARM SP805 watchdog module
31 #include <linux/watchdog.h>
36 #define MODULE_NAME "sp805-wdt"
38 /* watchdog register offsets and masks */
80 "Set to 1 to keep watchdog running after device release");
86 u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL); in wdt_is_running()
97 rate = wdt->rate; in wdt_setload()
105 load = div_u64(rate, 2) * timeout - 1; in wdt_setload()
[all …]
/openbmc/linux/Documentation/arch/mips/
H A Dingenic-tcu.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
9 counters, timers, or PWM.
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
[all …]
/openbmc/linux/kernel/time/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 # Watchdog function for clocksources to detect instabilities
21 # cycle update - x86/TSC misfeature
33 # Architecture can handle broadcast in a driver-agnostic way
51 # Select to handle posix CPU timers from task_work
86 menu "Timers subsystem"
113 will only trigger on an as-needed basis when the system is idle.
139 the expense of some overhead in user <-> kernel transitions:
163 The major pre-requirement for full dynticks to work is to
200 int "Clocksource watchdog maximum allowable skew (in μs)"
[all …]
/openbmc/linux/arch/sparc/include/uapi/asm/
H A Dwatchdog.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * watchdog - Driver interface for the hardware watchdog timers
14 #include <linux/watchdog.h>
16 /* Solaris compatibility ioctls--
17 * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
/openbmc/linux/drivers/acpi/arm64/
H A Dgtdt.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * struct acpi_gtdt_descriptor - Store the key info of GTDT for all functions
43 platform_timer += gh->length; in next_platform_timer()
58 return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK; in is_timer_block()
66 if (gh->type != ACPI_GTDT_TYPE_WATCHDOG) in is_non_secure_watchdog()
69 return !(wd->timer_flags & ACPI_GTDT_WATCHDOG_SECURE); in is_non_secure_watchdog()
86 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
90 * So we only handle the non-secure timer PPIs,
101 return map_gt_gsi(gtdt->non_secure_el1_interrupt, in acpi_gtdt_map_ppi()
102 gtdt->non_secure_el1_flags); in acpi_gtdt_map_ppi()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dralink,rt2880-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/ralink,rt2880-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink Watchdog Timers
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 - $ref: watchdog.yaml#
17 const: ralink,rt2880-wdt
32 - compatible
33 - reg
[all …]
H A Dmediatek,mt7621-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/mediatek,mt7621-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink Watchdog Timers
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 - $ref: watchdog.yaml#
17 const: mediatek,mt7621-wdt
29 - compatible
30 - reg
[all …]
H A Dmaxim,max63xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/maxim,max63xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim 63xx Watchdog Timers
10 - $ref: watchdog.yaml#
11 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
14 - Marc Zyngier <maz@kernel.org>
15 - Linus Walleij <linus.walleij@linaro.org>
20 - maxim,max6369
[all …]
H A Dmarvell,cn10624-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Global Timer (GTI) system watchdog
10 - Bharat Bhushan <bbhushan2@marvell.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - marvell,cn9670-wdt
20 - marvell,cn10624-wdt
[all …]
H A Datmel,at91sam9-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Atmel Watchdog Timers
11 - Eugen Hristev <eugen.hristev@microchip.com>
15 const: atmel,at91sam9260-wdt
26 atmel,max-heartbeat-sec:
32 atmel,min-heartbeat-sec:
35 must be smaller than the max-heartbeat-sec value. It is used to
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dbrcm,twd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom's Timer-Watchdog (aka TWD)
10 - Rafał Miłecki <rafal@milecki.pl>
13 Broadcom has a Timer-Watchdog block used in multiple SoCs (e.g., BCM4908,
15 registers layout). This block consists of: timers, watchdog and optionally a
21 - enum:
22 - brcm,bcm4908-twd
23 - brcm,bcm7038-twd
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
12 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
13 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
17 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
21 #include <watchdog.h>
39 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); in init_fbcs()
40 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); in init_fbcs()
41 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); in init_fbcs()
47 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); in init_fbcs()
[all …]
/openbmc/linux/Documentation/watchdog/
H A Dwdt.rst2 WDT Watchdog Timer Interfaces For The Linux Operating System
9 - ICS WDT501-P
10 - ICS WDT501-P (no fan tachometer)
11 - ICS WDT500-P
13 All the interfaces provide /dev/watchdog, which when open must be written
15 time another timeout. In the case of the software watchdog the ability to
17 boards physically pull the machine down off their own onboard timers and
26 The ICS ISA-bus wdt card cannot be safely probed for. Instead you need to
34 heartbeat Watchdog heartbeat in seconds (default 60)
35 nowayout Watchdog cannot be stopped once started (kernel
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
34 * ARM Timers Registers Map
36 #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
37 #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
38 #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
41 * ARM Timers Control Register
55 * ARM Timer\Watchdog Reload Register
62 * ARM Timer\Watchdog Register
78 #define timestamp gd->arch.tbl
[all …]
/openbmc/linux/arch/x86/platform/intel-mid/
H A Dintel-mid.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include <asm/intel-mid.h>
52 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; in intel_mid_time_init()
80 * watchdog or lock debug. Reading io port 0x61 results in 0xff which
97 x86_init.timers.timer_init = intel_mid_time_init; in x86_intel_mid_early_setup()
98 x86_init.timers.setup_percpu_clockev = x86_init_noop; in x86_intel_mid_early_setup()
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2002
8 #include <watchdog.h>
23 memctl8xx_t __iomem *memctl = &immr->im_memctl; in cpu_init_f()
26 /* SYPCR - contains watchdog control (11-9) */ in cpu_init_f()
29 /* deactivate watchdog if not enabled in config */ in cpu_init_f()
30 out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); in cpu_init_f()
35 /* SIUMCR - contains debug pin configuration (11-6) */ in cpu_init_f()
36 setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR); in cpu_init_f()
37 /* initialize timebase status and control register (11-26) */ in cpu_init_f()
[all …]

123456789